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Lesson 02 - Exercise 02
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‎exercises/lesson02/2/szediwy/include/entry.h‎

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#ifndef _ENTRY_H
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#define _ENTRY_H
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#define S_FRAME_SIZE 256 // size of all saved registers
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#define SYNC_INVALID_EL1t 0
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#define IRQ_INVALID_EL1t 1
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#define FIQ_INVALID_EL1t 2
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#define ERROR_INVALID_EL1t 3
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#define SYNC_INVALID_EL1h 4
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#define IRQ_INVALID_EL1h 5
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#define FIQ_INVALID_EL1h 6
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#define ERROR_INVALID_EL1h 7
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#define SYNC_INVALID_EL0_64 8
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#define IRQ_INVALID_EL0_64 9
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#define FIQ_INVALID_EL0_64 10
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#define ERROR_INVALID_EL0_64 11
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#define SYNC_INVALID_EL0_32 12
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#define IRQ_INVALID_EL0_32 13
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#define FIQ_INVALID_EL0_32 14
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#define ERROR_INVALID_EL0_32 15
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#endif

‎exercises/lesson02/2/szediwy/include/irq.h‎

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#ifndef _IRQ_H
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#define _IRQ_H
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void enable_interrupt_controller( void );
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void irq_vector_init( void );
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void enable_irq( void );
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void disable_irq( void );
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#endif /*_IRQ_H */

‎exercises/lesson02/2/szediwy/include/peripherals/base.h‎

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// 0x7E000000 (legacy) -> 0x4_7E00_0000 (35-bit) -> 0x0_FE00_0000 (low peripheral)
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#define PBASE 0xFE000000
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// The base address of the GIC-400 is 0x4c0040000. Note that, unlike other peripheral addresses in this document, this is an
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// ARM-only address and not a legacy master address. If Low Peripheral mode is enabled this base address becomes
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// 0xff840000.
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// The GIC-400 is configured with "NUM_CPUS=4" and "NUM_SPIS=192". For full register details, please refer to the ARM
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// GIC-400 documentation on the ARM Developer website.
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#define GIC_BASE 0xFF840000
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// The ARMC register base address is 0x7e00b000 -> 0x4_7E00B000 -> 0x0FE00B000
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#define ARMC_BASE 0x0FE00B000
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#endif /*_P_BASE_H */

‎exercises/lesson02/2/szediwy/include/peripherals/irq.h‎

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#ifndef _P_IRQ_H
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#define _P_IRQ_H
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#include "peripherals/base.h"
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#define IRQ_PENDING_0_CORE_0 (PBASE+0x0000B200)
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#define IRQ_PENDING_1_CORE_0 (PBASE+0x0000B204)
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#define IRQ_PENDING_2_CORE_0 (PBASE+0x0000B208)
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//#define FIQ_CONTROL (PBASE+0x0000B20C)
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#define ENABLE_IRQS_0_CORE_0 (PBASE+0x0000B210)
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#define ENABLE_IRQS_1_CORE_0 (PBASE+0x0000B214)
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#define ENABLE_IRQS_2_CORE_0 (PBASE+0x0000B218)
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#define DISABLE_IRQS_0_CORE_0 (PBASE+0x0000B220)
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#define DISABLE_IRQS_1_CORE_0 (PBASE+0x0000B224)
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#define DISABLE_IRQS_2_CORE_0 (PBASE+0x0000B228)
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#define SYSTEM_TIMER_IRQ_0 (1 << 0)
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#define SYSTEM_TIMER_IRQ_1 (1 << 1)
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#define SYSTEM_TIMER_IRQ_2 (1 << 2)
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#define SYSTEM_TIMER_IRQ_3 (1 << 3)
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#endif /*_P_IRQ_H */

‎exercises/lesson02/2/szediwy/include/peripherals/timer.h‎

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#ifndef _P_TIMER_H
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#define _P_TIMER_H
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#include "peripherals/base.h"
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#define TIMER_CS (PBASE+0x00003000)
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#define TIMER_CLO (PBASE+0x00003004)
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#define TIMER_CHI (PBASE+0x00003008)
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#define TIMER_C0 (PBASE+0x0000300C)
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#define TIMER_C1 (PBASE+0x00003010)
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#define TIMER_C2 (PBASE+0x00003014)
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#define TIMER_C3 (PBASE+0x00003018)
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#define TIMER_CS_M0 (1 << 0)
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#define TIMER_CS_M1 (1 << 1)
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#define TIMER_CS_M2 (1 << 2)
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#define TIMER_CS_M3 (1 << 3)
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#endif /*_P_TIMER_H */

‎exercises/lesson02/2/szediwy/include/timer.h‎

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#ifndef _TIMER_H
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#define _TIMER_H
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void timer_init ( void );
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void handle_timer_irq ( void );
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#endif /*_TIMER_H */

‎exercises/lesson02/2/szediwy/src/entry.S‎

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#include "entry.h"
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.macro handle_invalid_entry type
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kernel_entry
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mov x0, #\type
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mrs x1, esr_el1
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mrs x2, elr_el1
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bl show_invalid_entry_message
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b err_hang
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.endm
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.macro ventry label
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.align 7
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b \label
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.endm
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.macro kernel_entry
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sub sp, sp, #S_FRAME_SIZE
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stp x0, x1, [sp, #16 * 0]
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stp x2, x3, [sp, #16 * 1]
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stp x4, x5, [sp, #16 * 2]
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stp x6, x7, [sp, #16 * 3]
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stp x8, x9, [sp, #16 * 4]
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stp x10, x11, [sp, #16 * 5]
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stp x12, x13, [sp, #16 * 6]
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stp x14, x15, [sp, #16 * 7]
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stp x16, x17, [sp, #16 * 8]
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stp x18, x19, [sp, #16 * 9]
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stp x20, x21, [sp, #16 * 10]
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stp x22, x23, [sp, #16 * 11]
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stp x24, x25, [sp, #16 * 12]
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stp x26, x27, [sp, #16 * 13]
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stp x28, x29, [sp, #16 * 14]
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str x30, [sp, #16 * 15]
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.endm
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.macro kernel_exit
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ldp x0, x1, [sp, #16 * 0]
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ldp x2, x3, [sp, #16 * 1]
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ldp x4, x5, [sp, #16 * 2]
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ldp x6, x7, [sp, #16 * 3]
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ldp x8, x9, [sp, #16 * 4]
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ldp x10, x11, [sp, #16 * 5]
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ldp x12, x13, [sp, #16 * 6]
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ldp x14, x15, [sp, #16 * 7]
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ldp x16, x17, [sp, #16 * 8]
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ldp x18, x19, [sp, #16 * 9]
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ldp x20, x21, [sp, #16 * 10]
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ldp x22, x23, [sp, #16 * 11]
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ldp x24, x25, [sp, #16 * 12]
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ldp x26, x27, [sp, #16 * 13]
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ldp x28, x29, [sp, #16 * 14]
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ldr x30, [sp, #16 * 15]
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add sp, sp, #S_FRAME_SIZE
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eret
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.endm
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/*
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* Exception vectors.
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*/
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.align 11
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.globl vectors
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vectors:
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ventry sync_invalid_el1t // Synchronous EL1t
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ventry irq_invalid_el1t // IRQ EL1t
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ventry fiq_invalid_el1t // FIQ EL1t
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ventry error_invalid_el1t // Error EL1t
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ventry sync_invalid_el1h // Synchronous EL1h
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ventry el1_irq // IRQ EL1h
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ventry fiq_invalid_el1h // FIQ EL1h
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ventry error_invalid_el1h // Error EL1h
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ventry sync_invalid_el0_64 // Synchronous 64-bit EL0
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ventry irq_invalid_el0_64 // IRQ 64-bit EL0
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ventry fiq_invalid_el0_64 // FIQ 64-bit EL0
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ventry error_invalid_el0_64 // Error 64-bit EL0
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ventry sync_invalid_el0_32 // Synchronous 32-bit EL0
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ventry irq_invalid_el0_32 // IRQ 32-bit EL0
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ventry fiq_invalid_el0_32 // FIQ 32-bit EL0
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ventry error_invalid_el0_32 // Error 32-bit EL0
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sync_invalid_el1t:
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handle_invalid_entry SYNC_INVALID_EL1t
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irq_invalid_el1t:
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handle_invalid_entry IRQ_INVALID_EL1t
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fiq_invalid_el1t:
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handle_invalid_entry FIQ_INVALID_EL1t
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error_invalid_el1t:
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handle_invalid_entry ERROR_INVALID_EL1t
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sync_invalid_el1h:
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handle_invalid_entry SYNC_INVALID_EL1h
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fiq_invalid_el1h:
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handle_invalid_entry FIQ_INVALID_EL1h
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error_invalid_el1h:
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handle_invalid_entry ERROR_INVALID_EL1h
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sync_invalid_el0_64:
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handle_invalid_entry SYNC_INVALID_EL0_64
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irq_invalid_el0_64:
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handle_invalid_entry IRQ_INVALID_EL0_64
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fiq_invalid_el0_64:
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handle_invalid_entry FIQ_INVALID_EL0_64
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error_invalid_el0_64:
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handle_invalid_entry ERROR_INVALID_EL0_64
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sync_invalid_el0_32:
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handle_invalid_entry SYNC_INVALID_EL0_32
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irq_invalid_el0_32:
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handle_invalid_entry IRQ_INVALID_EL0_32
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fiq_invalid_el0_32:
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handle_invalid_entry FIQ_INVALID_EL0_32
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error_invalid_el0_32:
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handle_invalid_entry ERROR_INVALID_EL0_32
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el1_irq:
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kernel_entry
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bl handle_irq
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kernel_exit
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.globl err_hang
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err_hang: b err_hang

‎exercises/lesson02/2/szediwy/src/irq.S‎

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.globl irq_vector_init
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irq_vector_init:
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adr x0, vectors // load VBAR_EL1 with virtual
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msr vbar_el1, x0 // vector table address
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ret
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.globl enable_irq
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enable_irq:
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msr daifclr, #2
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ret
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.globl disable_irq
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disable_irq:
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msr daifset, #2
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ret

‎exercises/lesson02/2/szediwy/src/irq.c‎

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#include "utils.h"
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#include "printf.h"
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#include "timer.h"
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#include "entry.h"
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#include "peripherals/irq.h"
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const char *entry_error_messages[] = {
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"SYNC_INVALID_EL1t",
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"IRQ_INVALID_EL1t",
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"FIQ_INVALID_EL1t",
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"ERROR_INVALID_EL1T",
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"SYNC_INVALID_EL1h",
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"IRQ_INVALID_EL1h",
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"FIQ_INVALID_EL1h",
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"ERROR_INVALID_EL1h",
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"SYNC_INVALID_EL0_64",
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"IRQ_INVALID_EL0_64",
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"FIQ_INVALID_EL0_64",
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"ERROR_INVALID_EL0_64",
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"SYNC_INVALID_EL0_32",
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"IRQ_INVALID_EL0_32",
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"FIQ_INVALID_EL0_32",
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"ERROR_INVALID_EL0_32"
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};
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void enable_interrupt_controller()
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{
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put32(ENABLE_IRQS_0_CORE_0, SYSTEM_TIMER_IRQ_1);
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}
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void show_invalid_entry_message(int type, unsigned long esr, unsigned long address)
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{
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printf("%s, ESR: %x, address: %x\r\n", entry_error_messages[type], esr, address);
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}
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void handle_irq(void)
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{
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unsigned int irq = get32(IRQ_PENDING_0_CORE_0);
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switch (irq) {
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case (SYSTEM_TIMER_IRQ_1):
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handle_timer_irq();
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break;
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default:
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printf("Unknown pending irq: %x\r\n", irq);
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}
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}

‎exercises/lesson02/2/szediwy/src/kernel.c‎

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#include "custom_printf.h"
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#include "timer.h"
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#include "utils.h"
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#include "mini_uart.h"
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#include "irq.h"
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void kernel_main(unsigned long processor_index)
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{
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if (processor_index == 0)
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{
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uart_init();
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init_printf(0, putc);
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init_printf(0, putc);
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irq_vector_init();
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timer_init();
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enable_interrupt_controller();
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enable_irq();
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}
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while (processor_index != current_processor_index)

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