This repository contains RISC-V assembly code simulations developed and tested using the Ripes Simulator, a visual computer architecture simulator for educational purposes.
RISC-V is an open standard Reduced Instruction Set Computing (RISC) instruction set architecture (ISA) that is free and extensible. It is designed to be simple, modular, and efficient, making it ideal for teaching computer architecture as well as for commercial implementations.
Ripes is a user-friendly graphical simulator that allows users to:
- Visualize RISC-V pipelines
- Simulate assembly programs step-by-step
- Inspect registers, memory, and control signals
- Experiment with computer architecture concepts interactively
You can try the online version of Ripes here:
https://ripes.me/
The repository is organized into 24 folders, each named to indicate the covered topic for easy navigation:
riscv-ripes-simulator
โโโ 01_addition
โโโ 02_subtraction
โโโ 03_add_sub
โโโ 04_hll_to_alp
โโโ 05_imm_operand
โโโ 06_initialising
โโโ 07_32bit_load
โโโ 08_32bit_neg_load
โโโ 09_reading_mem
โโโ 10_storing_mem
โโโ 11_if_statement
โโโ 12_if_else
โโโ 13_case
โโโ 14_while
โโโ 15_do_while
โโโ 16_for
โโโ 17_array
โโโ 18_lb_sb_ascii
โโโ 19_func_call_return
โโโ 20_reg_on_stack
โโโ 21_scratch_reg_stack
โโโ 22_opt_func_call
โโโ 23_non_leaf_func
โโโ 24_factorial
โโโ LICENSE
โโโ README.md
-
Register_initialization ๐ ๏ธ
Instructions likeaddi,lui, setting registers with immediate values. -
Memory_load_store ๐พ
Loading and storing data withlw,sw,lb,sb. -
Control_flow_branching ๐
Branch instructionsbeq,bne, jump instructions, if-else clauses. -
Loops_iterations ๐
Common loops in assembly:for,while,do-while. -
Function_calls_stack ๐๐๏ธ
Stack frame creation, saving/restoring registers, calling conventions. -
Arithmetic_logic โโโ๏ธ
Arithmetic and logical operations:add,sub,mul, shifts. -
Character_array_manipulation ๐ค๐งฎ
Byte-level manipulations, ASCII case conversions. -
Recursive_algorithms โป๏ธ
Recursive functions like factorial with stack usage.
... and more.
- Navigate to folders corresponding to the topic of interest.
- Inside each folder, find RISC-V assembly code along with markdown explanations.
- Use the online or desktop Ripes simulator to load and run these codes.
- Modify and experiment with the code snippets to deepen your understanding.
- Ripes GitHub Repository
- Ripes Online Simulator
- Reference Book: The RISC-V Reader: An Open Architecture Atlas by Sarah Harris and David Harris
Happy learning and simulating RISC-V! ๐