@@ -900,14 +900,6 @@ unsigned char *(*rans_enc_func(int do_simd, int order))
900900 unsigned char * out ,
901901 unsigned int * out_size ) {
902902
903- int have_e_sse4_1 = have_sse4_1 ;
904- int have_e_avx2 = have_avx2 ;
905- int have_e_avx512f = have_avx512f ;
906-
907- if (!(rans_cpu & RANS_CPU_ENC_AVX512 )) have_e_avx512f = 0 ;
908- if (!(rans_cpu & RANS_CPU_ENC_AVX2 )) have_e_avx2 = 0 ;
909- if (!(rans_cpu & RANS_CPU_ENC_SSE4 )) have_e_sse4_1 = 0 ;
910-
911903 if (!do_simd ) { // SIMD disabled
912904 return order & 1
913905 ? rans_compress_O1_4x16
@@ -925,6 +917,14 @@ unsigned char *(*rans_enc_func(int do_simd, int order))
925917 }
926918#endif
927919
920+ int have_e_sse4_1 = have_sse4_1 ;
921+ int have_e_avx2 = have_avx2 ;
922+ int have_e_avx512f = have_avx512f ;
923+
924+ if (!(rans_cpu & RANS_CPU_ENC_AVX512 )) have_e_avx512f = 0 ;
925+ if (!(rans_cpu & RANS_CPU_ENC_AVX2 )) have_e_avx2 = 0 ;
926+ if (!(rans_cpu & RANS_CPU_ENC_SSE4 )) have_e_sse4_1 = 0 ;
927+
928928 if (order & 1 ) {
929929 // With simulated gathers, the AVX512 is now slower than AVX2, so
930930 // we avoid using it unless asking for the real avx512 gather.
@@ -974,14 +974,6 @@ unsigned char *(*rans_dec_func(int do_simd, int order))
974974 unsigned char * out ,
975975 unsigned int out_size ) {
976976
977- int have_d_sse4_1 = have_sse4_1 ;
978- int have_d_avx2 = have_avx2 ;
979- int have_d_avx512f = have_avx512f ;
980-
981- if (!(rans_cpu & RANS_CPU_DEC_AVX512 )) have_d_avx512f = 0 ;
982- if (!(rans_cpu & RANS_CPU_DEC_AVX2 )) have_d_avx2 = 0 ;
983- if (!(rans_cpu & RANS_CPU_DEC_SSE4 )) have_d_sse4_1 = 0 ;
984-
985977 if (!do_simd ) { // SIMD disabled
986978 return order & 1
987979 ? rans_uncompress_O1_4x16
@@ -999,6 +991,14 @@ unsigned char *(*rans_dec_func(int do_simd, int order))
999991 }
1000992#endif
1001993
994+ int have_d_sse4_1 = have_sse4_1 ;
995+ int have_d_avx2 = have_avx2 ;
996+ int have_d_avx512f = have_avx512f ;
997+
998+ if (!(rans_cpu & RANS_CPU_DEC_AVX512 )) have_d_avx512f = 0 ;
999+ if (!(rans_cpu & RANS_CPU_DEC_AVX2 )) have_d_avx2 = 0 ;
1000+ if (!(rans_cpu & RANS_CPU_DEC_SSE4 )) have_d_sse4_1 = 0 ;
1001+
10021002 if (order & 1 ) {
10031003#if defined(HAVE_AVX512 )
10041004 if (have_d_avx512f )
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