Skip to content

Commit 096821a

Browse files
skip next_access update in fulltracer (#1217)
tested with block num `23817600` e2e (with recursion) | Component | Before Time | After Time | Improvement | |-------------|-------------|------------|-------------| | reth-block | 153 s | 141 s | ↓ 7.8% | | app.prove | 150 s | 138 s | ↓ 8.0% | Co-authored-by: xkx <[email protected]>
1 parent ce97cf8 commit 096821a

File tree

2 files changed

+21
-18
lines changed

2 files changed

+21
-18
lines changed

ceno_emul/src/tracer.rs

Lines changed: 11 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ use crate::{
88
};
99
use ceno_rt::WORD_SIZE;
1010
use smallvec::SmallVec;
11-
use std::{collections::BTreeMap, fmt, mem};
11+
use std::{collections::BTreeMap, fmt, mem, sync::Arc};
1212

1313
/// An instruction and its context in an execution trace. That is concrete values of registers and memory.
1414
///
@@ -88,6 +88,14 @@ pub trait Tracer {
8888

8989
fn new(platform: &Platform) -> Self;
9090

91+
fn with_next_accesses(platform: &Platform, next_accesses: Option<Arc<NextCycleAccess>>) -> Self
92+
where
93+
Self: Sized,
94+
{
95+
let _ = next_accesses;
96+
Self::new(platform)
97+
}
98+
9199
fn advance(&mut self) -> Self::Record;
92100

93101
fn is_busy_loop(&self, record: &Self::Record) -> bool;
@@ -541,10 +549,6 @@ pub struct FullTracer {
541549

542550
// keep track of each address that the cycle when they were last accessed.
543551
latest_accesses: LatestAccesses,
544-
545-
// keep track of each cycle that accessed addresses in the future with respective future cycles.
546-
// format: [current cycle -> Vec<(WordAddr, Cycle)>]
547-
next_accesses: NextCycleAccess,
548552
}
549553

550554
impl FullTracer {
@@ -565,7 +569,6 @@ impl FullTracer {
565569
},
566570
platform: platform.clone(),
567571
latest_accesses: LatestAccesses::new(platform),
568-
next_accesses: NextCycleAccess::new(ACCESSED_CHUNK_SIZE),
569572
max_heap_addr_access: ByteAddr::from(platform.heap.start),
570573
max_hint_addr_access: ByteAddr::from(platform.hints.start),
571574
}
@@ -711,21 +714,13 @@ impl FullTracer {
711714
#[inline(always)]
712715
pub fn track_access(&mut self, addr: WordAddr, subcycle: Cycle) -> Cycle {
713716
let cur_cycle = self.record.cycle + subcycle;
714-
let prev_cycle = self.latest_accesses.track(addr, cur_cycle);
715-
self.next_accesses
716-
.get_or_create(prev_cycle as usize)
717-
.push((addr, cur_cycle));
718-
prev_cycle
717+
self.latest_accesses.track(addr, cur_cycle)
719718
}
720719

721720
pub fn final_accesses(&self) -> &LatestAccesses {
722721
&self.latest_accesses
723722
}
724723

725-
pub fn next_accesses(self) -> NextCycleAccess {
726-
self.next_accesses
727-
}
728-
729724
/// Return the cycle of the pending instruction (after the last completed step).
730725
pub fn cycle(&self) -> Cycle {
731726
self.record.cycle
@@ -1010,7 +1005,7 @@ impl Tracer for FullTracer {
10101005
}
10111006

10121007
fn into_next_accesses(self) -> NextCycleAccess {
1013-
self.next_accesses()
1008+
unimplemented!("FullTracer does not record next access metadata")
10141009
}
10151010

10161011
fn cycle(&self) -> Cycle {

ceno_emul/src/vm_state.rs

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use crate::{
66
platform::Platform,
77
rv32im::{Instruction, TrapCause},
88
syscalls::{SyscallEffects, handle_syscall},
9-
tracer::{Change, FullTracer, Tracer},
9+
tracer::{Change, FullTracer, NextCycleAccess, Tracer},
1010
};
1111
use anyhow::{Result, anyhow};
1212
use std::{iter::from_fn, ops::Deref, sync::Arc};
@@ -47,6 +47,14 @@ impl<T: Tracer> VMState<T> {
4747
pub const REG_COUNT: usize = VM_REG_COUNT;
4848

4949
pub fn new_with_tracer(platform: Platform, program: Arc<Program>) -> Self {
50+
Self::new_with_tracer_and_next_accesses(platform, program, None)
51+
}
52+
53+
pub fn new_with_tracer_and_next_accesses(
54+
platform: Platform,
55+
program: Arc<Program>,
56+
next_accesses: Option<Arc<NextCycleAccess>>,
57+
) -> Self {
5058
let pc = program.entry;
5159

5260
let mut vm = Self {
@@ -59,7 +67,7 @@ impl<T: Tracer> VMState<T> {
5967
),
6068
registers: [0; VM_REG_COUNT],
6169
halt_state: None,
62-
tracer: T::new(&platform),
70+
tracer: T::with_next_accesses(&platform, next_accesses),
6371
};
6472

6573
for (&addr, &value) in &program.image {

0 commit comments

Comments
 (0)