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record instret during prelight execution
1 parent ac5d1b4 commit af7382d

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32 files changed

+45
-2
lines changed

32 files changed

+45
-2
lines changed

crates/circuits/mod-builder/src/core_chip.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -425,6 +425,7 @@ where
425425
&mut adapter_record,
426426
);
427427

428+
*state.instret += 1;
428429
*state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
429430
Ok(())
430431
}

crates/vm/src/arch/execution.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -216,6 +216,7 @@ pub trait PreflightExecutor<F, RA = MatrixRecordArena<F>> {
216216
#[derive(derive_new::new)]
217217
pub struct VmStateMut<'a, F, MEM, RA> {
218218
pub pc: &'a mut u32,
219+
pub instret: &'a mut u64,
219220
pub memory: &'a mut MEM,
220221
pub streams: &'a mut Streams<F>,
221222
pub rng: &'a mut StdRng,

crates/vm/src/arch/state.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ impl<F: Clone, MEM> VmState<F, MEM> {
6767
pub fn into_mut<'a, RA>(&'a mut self, ctx: &'a mut RA) -> VmStateMut<'a, F, MEM, RA> {
6868
VmStateMut {
6969
pc: &mut self.pc,
70+
instret: &mut self.instret,
7071
memory: &mut self.memory,
7172
streams: &mut self.streams,
7273
rng: &mut self.rng,

crates/vm/src/arch/testing/cpu.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,10 @@ where
9898
tracing::debug!("initial_timestamp={}", self.memory.memory.timestamp());
9999

100100
let mut pc = initial_pc;
101+
let mut instret = 0;
101102
let state_mut = VmStateMut {
102103
pc: &mut pc,
104+
instret: &mut instret,
103105
memory: &mut self.memory.memory,
104106
streams: &mut self.streams,
105107
rng: &mut self.rng,

crates/vm/src/arch/testing/cuda.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,8 +132,10 @@ impl TestBuilder<F> for GpuChipTestBuilder {
132132
tracing::debug!("initial_timestamp={}", initial_state.timestamp);
133133

134134
let mut pc = initial_pc;
135+
let mut instret = 0;
135136
let state_mut = VmStateMut::new(
136137
&mut pc,
138+
&mut instret,
137139
&mut self.memory.memory,
138140
&mut self.streams,
139141
&mut self.rng,

crates/vm/src/system/phantom/mod.rs

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -157,14 +157,18 @@ where
157157
SysPhantom::CtStart => {
158158
let metrics = state.metrics;
159159
if let Some(info) = metrics.debug_infos.get(pc) {
160-
metrics.cycle_tracker.start(info.dsl_instruction.clone());
160+
metrics
161+
.cycle_tracker
162+
.start(info.dsl_instruction.clone(), *state.instret as usize);
161163
}
162164
}
163165
#[cfg(feature = "perf-metrics")]
164166
SysPhantom::CtEnd => {
165167
let metrics = state.metrics;
166168
if let Some(info) = metrics.debug_infos.get(pc) {
167-
metrics.cycle_tracker.end(info.dsl_instruction.clone());
169+
metrics
170+
.cycle_tracker
171+
.end(info.dsl_instruction.clone(), *state.instret as usize);
168172
}
169173
}
170174
_ => {}
@@ -187,6 +191,7 @@ where
187191
inner: err,
188192
})?;
189193
}
194+
*state.instret += 1;
190195
*state.pc += DEFAULT_PC_STEP;
191196
state.memory.increment_timestamp();
192197

crates/vm/src/system/public_values/core.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,7 @@ where
202202
}
203203
}
204204

205+
*state.instret += 1;
205206
*state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
206207

207208
Ok(())

extensions/keccak256/circuit/src/trace.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -235,6 +235,7 @@ where
235235
}
236236

237237
// Due to the AIR constraints, the final memory timestamp should be the following:
238+
*state.instret += 1;
238239
state.memory.timestamp = record.inner.timestamp
239240
+ (len + KECCAK_REGISTER_READS + KECCAK_ABSORB_READS + KECCAK_DIGEST_WRITES) as u32;
240241
*state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);

extensions/native/circuit/src/branch_eq/core.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,8 @@ where
7676
*state.pc = state.pc.wrapping_add(self.pc_step);
7777
}
7878

79+
*state.instret += 1;
80+
7981
Ok(())
8082
}
8183
}

extensions/native/circuit/src/castf/core.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -157,6 +157,7 @@ where
157157
self.adapter
158158
.write(state.memory, instruction, x, &mut adapter_record);
159159

160+
*state.instret += 1;
160161
*state.pc = state.pc.wrapping_add(DEFAULT_PC_STEP);
161162

162163
Ok(())

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