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Fix memory region for rock3b.
Signed-off-by: Jakub Duchniewicz <[email protected]>
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build_sdk.py

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Original file line numberDiff line numberDiff line change
@@ -274,7 +274,7 @@ class ConfigInfo:
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name="rock3b",
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arch=KernelArch.AARCH64,
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gcc_cpu="cortex-a55",
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loader_link_address=0x30000000, # TODO: double check
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loader_link_address=0x30000000,
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kernel_options={
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"KernelPlatform": "rk3568",
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} | DEFAULT_KERNEL_OPTIONS_AARCH64,

loader/src/loader.c

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@@ -307,7 +307,7 @@ static void putc(uint8_t ch)
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}
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#elif defined(BOARD_rock3b)
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#define UART_BASE 0xfdd50000
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#define UART_BASE 0xfe660000
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#define UTHR 0x0
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#define ULSR 0x14
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#define ULSR_THRE (1 << 5)

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