fix typo and set more reasonable branch misprediction latency penalty

Author: andrej

CustomStages/MCADFetchDelayStage.cpp

@@ -54,7 +54,7 @@ llvm::Error MCADFetchDelayStage::execute(llvm::mca::InstRef &IR) {
             LLVM_DEBUG(dbgs() << "[MCAD FetchDelayStage] Previous branch at "); 
             LLVM_DEBUG(dbgs().write_hex(instrAddr->addr));
             LLVM_DEBUG(dbgs() << " mispredicted, delaying next instruction by " 
-                       << delayCyclesLeft << "cycle(s).\n");
+                       << delayCyclesLeft << " cycle(s).\n");
         } else {
             LLVM_DEBUG(dbgs() << "[MCAD FetchDelayStage] Previous branch at ");
             LLVM_DEBUG(dbgs().write_hex(instrAddr->addr));

MCAWorker.cpp

@@ -182,7 +182,7 @@ std::unique_ptr<mca::Pipeline> MCAWorker::createDefaultPipeline() {
                                           MCAPO.StoreQueueSize,
                                           MCAPO.AssumeNoAlias, &MDRegistry);
   auto HWS = std::make_unique<Scheduler>(SM, *LSU);
-  auto BPU = std::make_unique<NaiveBranchPredictorUnit>(100);
+  auto BPU = std::make_unique<NaiveBranchPredictorUnit>(20);
 
   // Create the pipeline stages.
   auto Fetch = std::make_unique<EntryStage>(SrcMgr);
@@ -227,7 +227,7 @@ std::unique_ptr<mca::Pipeline> MCAWorker::createInOrderPipeline() {
   auto LSU = std::make_unique<MCADLSUnit>(SM, MCAPO.LoadQueueSize,
                                           MCAPO.StoreQueueSize,
                                           MCAPO.AssumeNoAlias, &MDRegistry);
-  auto BPU = std::make_unique<NaiveBranchPredictorUnit>(100);
+  auto BPU = std::make_unique<NaiveBranchPredictorUnit>(20);
 
   // Create the pipeline stages.
   auto Entry = std::make_unique<EntryStage>(SrcMgr);