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[X86] AMD Znver2 (Rome) Scheduler enablement
The patch gives out the details of the znver2 scheduler model. There are few improvements with respect to execution units, latencies and throughput when compared with znver1. The tests that were present for znver1 for llvm-mca tool were replicated. The latencies, execution units, timeline and throughput information are updated for znver2. Reviewers: craig.topper, Simon Pilgrim Differential Revision: https://reviews.llvm.org/D66088
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‎llvm/lib/Target/X86/X86.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -501,6 +501,7 @@ include "X86SchedHaswell.td"
501501
include "X86SchedBroadwell.td"
502502
include "X86ScheduleSLM.td"
503503
include "X86ScheduleZnver1.td"
504+
include "X86ScheduleZnver2.td"
504505
include "X86ScheduleBdVer2.td"
505506
include "X86ScheduleBtVer2.td"
506507
include "X86SchedSkylakeClient.td"
@@ -1204,7 +1205,7 @@ def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>;
12041205
def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>;
12051206

12061207
def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
1207-
def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
1208+
def : ProcessorModel<"znver2", Znver2Model, ProcessorFeatures.ZN2Features>;
12081209

12091210
def : Proc<"geode", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
12101211
Feature3DNowA, FeatureInsertVZEROUPPER]>;

‎llvm/lib/Target/X86/X86InstrInfo.td‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2851,7 +2851,7 @@ let SchedRW = [WriteStore], Defs = [EFLAGS] in {
28512851
//===----------------------------------------------------------------------===//
28522852
// CLZERO Instruction
28532853
//
2854-
let SchedRW = [WriteSystem] in {
2854+
let SchedRW = [WriteLoad] in {
28552855
let Uses = [EAX] in
28562856
def CLZERO32r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>,
28572857
TB, Requires<[HasCLZERO, Not64BitMode]>;

‎llvm/lib/Target/X86/X86ScheduleZnver2.td‎

Lines changed: 1548 additions & 0 deletions
Large diffs are not rendered by default.

‎llvm/test/MC/X86/x86_long_nop.s‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,8 @@
1313
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=btver2 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
1414
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver1 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
1515
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver1 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
16+
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=x86_64-pc-linux-gnu -mcpu=znver2 %s | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
17+
# RUN: llvm-mc -filetype=obj -arch=x86 -triple=i686-pc-linux-gnu %s -mcpu=znver2 | llvm-objdump -d -no-show-raw-insn - | FileCheck %s --check-prefix=LNOP15
1618

1719
# Ensure alignment directives also emit sequences of 10, 11 and 15-byte NOPs on processors
1820
# capable of using long NOPs.

‎llvm/test/tools/llvm-mca/X86/Generic/resources-clzero.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ clzero
1212
# CHECK-NEXT: [6]: HasSideEffects (U)
1313

1414
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
15-
# CHECK-NEXT: 1 100 0.33 U clzero
15+
# CHECK-NEXT: 1 5 0.50 U clzero
1616

1717
# CHECK: Resources:
1818
# CHECK-NEXT: [0] - SBDivider
@@ -26,8 +26,8 @@ clzero
2626

2727
# CHECK: Resource pressure per iteration:
2828
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1]
29-
# CHECK-NEXT: - - 0.33 0.33 - 0.33 - -
29+
# CHECK-NEXT: - - - - - - 0.50 0.50
3030

3131
# CHECK: Resource pressure by instruction:
3232
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6.0] [6.1] Instructions:
33-
# CHECK-NEXT: - - 0.33 0.33 - 0.33 - - clzero
33+
# CHECK-NEXT: - - - - - - 0.50 0.50 clzero

‎llvm/test/tools/llvm-mca/X86/Znver1/resources-clzero.s‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ clzero
1212
# CHECK-NEXT: [6]: HasSideEffects (U)
1313

1414
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
15-
# CHECK-NEXT: 1 100 0.25 U clzero
15+
# CHECK-NEXT: 1 8 0.50 U clzero
1616

1717
# CHECK: Resources:
1818
# CHECK-NEXT: [0] - ZnAGU0
@@ -30,8 +30,8 @@ clzero
3030

3131
# CHECK: Resource pressure per iteration:
3232
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
33-
# CHECK-NEXT: - - - - - - - - - - - -
33+
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - -
3434

3535
# CHECK: Resource pressure by instruction:
3636
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
37-
# CHECK-NEXT: - - - - - - - - - - - - clzero
37+
# CHECK-NEXT: 0.50 0.50 - - - - - - - - - - clzero

‎llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-2.s‎

Lines changed: 47 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
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# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2+
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
3+
4+
imul %rax, %rbx
5+
lzcnt %ax, %bx
6+
add %ecx, %ebx
7+
8+
# CHECK: Iterations: 1
9+
# CHECK-NEXT: Instructions: 3
10+
# CHECK-NEXT: Total Cycles: 9
11+
# CHECK-NEXT: Total uOps: 4
12+
13+
# CHECK: Dispatch Width: 4
14+
# CHECK-NEXT: uOps Per Cycle: 0.44
15+
# CHECK-NEXT: IPC: 0.33
16+
# CHECK-NEXT: Block RThroughput: 1.0
17+
18+
# CHECK: Instruction Info:
19+
# CHECK-NEXT: [1]: #uOps
20+
# CHECK-NEXT: [2]: Latency
21+
# CHECK-NEXT: [3]: RThroughput
22+
# CHECK-NEXT: [4]: MayLoad
23+
# CHECK-NEXT: [5]: MayStore
24+
# CHECK-NEXT: [6]: HasSideEffects (U)
25+
26+
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
27+
# CHECK-NEXT: 2 4 1.00 imulq %rax, %rbx
28+
# CHECK-NEXT: 1 1 0.25 lzcntw %ax, %bx
29+
# CHECK-NEXT: 1 1 0.25 addl %ecx, %ebx
30+
31+
# CHECK: Timeline view:
32+
# CHECK-NEXT: Index 012345678
33+
34+
# CHECK: [0,0] DeeeeER . imulq %rax, %rbx
35+
# CHECK-NEXT: [0,1] D====eER. lzcntw %ax, %bx
36+
# CHECK-NEXT: [0,2] D=====eER addl %ecx, %ebx
37+
38+
# CHECK: Average Wait times (based on the timeline view):
39+
# CHECK-NEXT: [0]: Executions
40+
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
41+
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
42+
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
43+
44+
# CHECK: [0] [1] [2] [3]
45+
# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulq %rax, %rbx
46+
# CHECK-NEXT: 1. 1 5.0 0.0 0.0 lzcntw %ax, %bx
47+
# CHECK-NEXT: 2. 1 6.0 0.0 0.0 addl %ecx, %ebx

‎llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-3.s‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2+
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1500 -timeline -timeline-max-iterations=6 < %s | FileCheck %s
3+
4+
# The ILP is limited by the false dependency on %dx. So, the mov cannot execute
5+
# in parallel with the add.
6+
7+
add %cx, %dx
8+
mov %ax, %dx
9+
xor %bx, %dx
10+
11+
# CHECK: Iterations: 1500
12+
# CHECK-NEXT: Instructions: 4500
13+
# CHECK-NEXT: Total Cycles: 4503
14+
# CHECK-NEXT: Total uOps: 4500
15+
16+
# CHECK: Dispatch Width: 4
17+
# CHECK-NEXT: uOps Per Cycle: 1.00
18+
# CHECK-NEXT: IPC: 1.00
19+
# CHECK-NEXT: Block RThroughput: 0.8
20+
21+
# CHECK: Instruction Info:
22+
# CHECK-NEXT: [1]: #uOps
23+
# CHECK-NEXT: [2]: Latency
24+
# CHECK-NEXT: [3]: RThroughput
25+
# CHECK-NEXT: [4]: MayLoad
26+
# CHECK-NEXT: [5]: MayStore
27+
# CHECK-NEXT: [6]: HasSideEffects (U)
28+
29+
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
30+
# CHECK-NEXT: 1 1 0.25 addw %cx, %dx
31+
# CHECK-NEXT: 1 1 0.25 movw %ax, %dx
32+
# CHECK-NEXT: 1 1 0.25 xorw %bx, %dx
33+
34+
# CHECK: Resources:
35+
# CHECK-NEXT: [0] - Zn2AGU0
36+
# CHECK-NEXT: [1] - Zn2AGU1
37+
# CHECK-NEXT: [2] - Zn2AGU2
38+
# CHECK-NEXT: [3] - Zn2ALU0
39+
# CHECK-NEXT: [4] - Zn2ALU1
40+
# CHECK-NEXT: [5] - Zn2ALU2
41+
# CHECK-NEXT: [6] - Zn2ALU3
42+
# CHECK-NEXT: [7] - Zn2Divider
43+
# CHECK-NEXT: [8] - Zn2FPU0
44+
# CHECK-NEXT: [9] - Zn2FPU1
45+
# CHECK-NEXT: [10] - Zn2FPU2
46+
# CHECK-NEXT: [11] - Zn2FPU3
47+
# CHECK-NEXT: [12] - Zn2Multiplier
48+
49+
# CHECK: Resource pressure per iteration:
50+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
51+
# CHECK-NEXT: - - - 0.75 0.75 0.75 0.75 - - - - - -
52+
53+
# CHECK: Resource pressure by instruction:
54+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
55+
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - addw %cx, %dx
56+
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - movw %ax, %dx
57+
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - xorw %bx, %dx
58+
59+
# CHECK: Timeline view:
60+
# CHECK-NEXT: 0123456789
61+
# CHECK-NEXT: Index 0123456789 0
62+
63+
# CHECK: [0,0] DeER . . . . addw %cx, %dx
64+
# CHECK-NEXT: [0,1] D=eER. . . . movw %ax, %dx
65+
# CHECK-NEXT: [0,2] D==eER . . . xorw %bx, %dx
66+
# CHECK-NEXT: [1,0] D===eER . . . addw %cx, %dx
67+
# CHECK-NEXT: [1,1] .D===eER . . . movw %ax, %dx
68+
# CHECK-NEXT: [1,2] .D====eER . . . xorw %bx, %dx
69+
# CHECK-NEXT: [2,0] .D=====eER. . . addw %cx, %dx
70+
# CHECK-NEXT: [2,1] .D======eER . . movw %ax, %dx
71+
# CHECK-NEXT: [2,2] . D======eER . . xorw %bx, %dx
72+
# CHECK-NEXT: [3,0] . D=======eER . . addw %cx, %dx
73+
# CHECK-NEXT: [3,1] . D========eER . . movw %ax, %dx
74+
# CHECK-NEXT: [3,2] . D=========eER. . xorw %bx, %dx
75+
# CHECK-NEXT: [4,0] . D=========eER . addw %cx, %dx
76+
# CHECK-NEXT: [4,1] . D==========eER . movw %ax, %dx
77+
# CHECK-NEXT: [4,2] . D===========eER . xorw %bx, %dx
78+
# CHECK-NEXT: [5,0] . D============eER . addw %cx, %dx
79+
# CHECK-NEXT: [5,1] . D============eER. movw %ax, %dx
80+
# CHECK-NEXT: [5,2] . D=============eER xorw %bx, %dx
81+
82+
# CHECK: Average Wait times (based on the timeline view):
83+
# CHECK-NEXT: [0]: Executions
84+
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
85+
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
86+
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
87+
88+
# CHECK: [0] [1] [2] [3]
89+
# CHECK-NEXT: 0. 6 7.0 0.2 0.0 addw %cx, %dx
90+
# CHECK-NEXT: 1. 6 7.7 0.0 0.0 movw %ax, %dx
91+
# CHECK-NEXT: 2. 6 8.5 0.0 0.0 xorw %bx, %dx

‎llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-4.s‎

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1+
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2+
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1500 -timeline -timeline-max-iterations=7 < %s | FileCheck %s
3+
4+
# The lzcnt cannot execute in parallel with the imul because there is a false
5+
# dependency on %bx.
6+
7+
imul %ax, %bx
8+
lzcnt %ax, %bx
9+
add %cx, %bx
10+
11+
# CHECK: Iterations: 1500
12+
# CHECK-NEXT: Instructions: 4500
13+
# CHECK-NEXT: Total Cycles: 7503
14+
# CHECK-NEXT: Total uOps: 4500
15+
16+
# CHECK: Dispatch Width: 4
17+
# CHECK-NEXT: uOps Per Cycle: 0.60
18+
# CHECK-NEXT: IPC: 0.60
19+
# CHECK-NEXT: Block RThroughput: 1.0
20+
21+
# CHECK: Instruction Info:
22+
# CHECK-NEXT: [1]: #uOps
23+
# CHECK-NEXT: [2]: Latency
24+
# CHECK-NEXT: [3]: RThroughput
25+
# CHECK-NEXT: [4]: MayLoad
26+
# CHECK-NEXT: [5]: MayStore
27+
# CHECK-NEXT: [6]: HasSideEffects (U)
28+
29+
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
30+
# CHECK-NEXT: 1 3 1.00 imulw %ax, %bx
31+
# CHECK-NEXT: 1 1 0.25 lzcntw %ax, %bx
32+
# CHECK-NEXT: 1 1 0.25 addw %cx, %bx
33+
34+
# CHECK: Resources:
35+
# CHECK-NEXT: [0] - Zn2AGU0
36+
# CHECK-NEXT: [1] - Zn2AGU1
37+
# CHECK-NEXT: [2] - Zn2AGU2
38+
# CHECK-NEXT: [3] - Zn2ALU0
39+
# CHECK-NEXT: [4] - Zn2ALU1
40+
# CHECK-NEXT: [5] - Zn2ALU2
41+
# CHECK-NEXT: [6] - Zn2ALU3
42+
# CHECK-NEXT: [7] - Zn2Divider
43+
# CHECK-NEXT: [8] - Zn2FPU0
44+
# CHECK-NEXT: [9] - Zn2FPU1
45+
# CHECK-NEXT: [10] - Zn2FPU2
46+
# CHECK-NEXT: [11] - Zn2FPU3
47+
# CHECK-NEXT: [12] - Zn2Multiplier
48+
49+
# CHECK: Resource pressure per iteration:
50+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
51+
# CHECK-NEXT: - - 0.67 1.00 0.67 0.67 - - - - - 1.00
52+
53+
# CHECK: Resource pressure by instruction:
54+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
55+
# CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 imulw %ax, %bx
56+
# CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - lzcntw %ax, %bx
57+
# CHECK-NEXT: - - 0.33 - 0.33 0.33 - - - - - - addw %cx, %bx
58+
59+
# CHECK: Timeline view:
60+
# CHECK-NEXT: 0123456789 01234567
61+
# CHECK-NEXT: Index 0123456789 0123456789
62+
63+
# CHECK: [0,0] DeeeER . . . . . . . imulw %ax, %bx
64+
# CHECK-NEXT: [0,1] D===eER . . . . . . . lzcntw %ax, %bx
65+
# CHECK-NEXT: [0,2] D====eER . . . . . . . addw %cx, %bx
66+
# CHECK-NEXT: [1,0] D=====eeeER . . . . . . imulw %ax, %bx
67+
# CHECK-NEXT: [1,1] .D=======eER . . . . . . lzcntw %ax, %bx
68+
# CHECK-NEXT: [1,2] .D========eER . . . . . . addw %cx, %bx
69+
# CHECK-NEXT: [2,0] .D=========eeeER . . . . . imulw %ax, %bx
70+
# CHECK-NEXT: [2,1] .D============eER . . . . . lzcntw %ax, %bx
71+
# CHECK-NEXT: [2,2] . D============eER . . . . . addw %cx, %bx
72+
# CHECK-NEXT: [3,0] . D=============eeeER . . . . imulw %ax, %bx
73+
# CHECK-NEXT: [3,1] . D================eER . . . . lzcntw %ax, %bx
74+
# CHECK-NEXT: [3,2] . D=================eER . . . . addw %cx, %bx
75+
# CHECK-NEXT: [4,0] . D=================eeeER . . . imulw %ax, %bx
76+
# CHECK-NEXT: [4,1] . D====================eER . . . lzcntw %ax, %bx
77+
# CHECK-NEXT: [4,2] . D=====================eER . . . addw %cx, %bx
78+
# CHECK-NEXT: [5,0] . D======================eeeER . . imulw %ax, %bx
79+
# CHECK-NEXT: [5,1] . D========================eER . . lzcntw %ax, %bx
80+
# CHECK-NEXT: [5,2] . D=========================eER . . addw %cx, %bx
81+
# CHECK-NEXT: [6,0] . D==========================eeeER . imulw %ax, %bx
82+
# CHECK-NEXT: [6,1] . D=============================eER. lzcntw %ax, %bx
83+
# CHECK-NEXT: [6,2] . D=============================eER addw %cx, %bx
84+
85+
# CHECK: Average Wait times (based on the timeline view):
86+
# CHECK-NEXT: [0]: Executions
87+
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
88+
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
89+
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
90+
91+
# CHECK: [0] [1] [2] [3]
92+
# CHECK-NEXT: 0. 7 14.1 0.1 0.0 imulw %ax, %bx
93+
# CHECK-NEXT: 1. 7 16.9 0.0 0.0 lzcntw %ax, %bx
94+
# CHECK-NEXT: 2. 7 17.6 0.0 0.0 addw %cx, %bx

‎llvm/test/tools/llvm-mca/X86/Znver2/partial-reg-update-5.s‎

Lines changed: 70 additions & 0 deletions
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1+
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
2+
# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver2 -iterations=1500 -timeline -timeline-max-iterations=8 < %s | FileCheck %s
3+
4+
lzcnt %ax, %bx ## partial register stall.
5+
6+
# CHECK: Iterations: 1500
7+
# CHECK-NEXT: Instructions: 1500
8+
# CHECK-NEXT: Total Cycles: 1503
9+
# CHECK-NEXT: Total uOps: 1500
10+
11+
# CHECK: Dispatch Width: 4
12+
# CHECK-NEXT: uOps Per Cycle: 1.00
13+
# CHECK-NEXT: IPC: 1.00
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# CHECK-NEXT: Block RThroughput: 0.3
15+
16+
# CHECK: Instruction Info:
17+
# CHECK-NEXT: [1]: #uOps
18+
# CHECK-NEXT: [2]: Latency
19+
# CHECK-NEXT: [3]: RThroughput
20+
# CHECK-NEXT: [4]: MayLoad
21+
# CHECK-NEXT: [5]: MayStore
22+
# CHECK-NEXT: [6]: HasSideEffects (U)
23+
24+
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
25+
# CHECK-NEXT: 1 1 0.25 lzcntw %ax, %bx
26+
27+
# CHECK: Resources:
28+
# CHECK-NEXT: [0] - Zn2AGU0
29+
# CHECK-NEXT: [1] - Zn2AGU1
30+
# CHECK-NEXT: [2] - Zn2AGU2
31+
# CHECK-NEXT: [3] - Zn2ALU0
32+
# CHECK-NEXT: [4] - Zn2ALU1
33+
# CHECK-NEXT: [5] - Zn2ALU2
34+
# CHECK-NEXT: [6] - Zn2ALU3
35+
# CHECK-NEXT: [7] - Zn2Divider
36+
# CHECK-NEXT: [8] - Zn2FPU0
37+
# CHECK-NEXT: [9] - Zn2FPU1
38+
# CHECK-NEXT: [10] - Zn2FPU2
39+
# CHECK-NEXT: [11] - Zn2FPU3
40+
# CHECK-NEXT: [12] - Zn2Multiplier
41+
42+
# CHECK: Resource pressure per iteration:
43+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
44+
# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - -
45+
46+
# CHECK: Resource pressure by instruction:
47+
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] Instructions:
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# CHECK-NEXT: - - 0.25 0.25 0.25 0.25 - - - - - - lzcntw %ax, %bx
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50+
# CHECK: Timeline view:
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# CHECK-NEXT: 0
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# CHECK-NEXT: Index 0123456789
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# CHECK: [0,0] DeER . . lzcntw %ax, %bx
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# CHECK-NEXT: [1,0] D=eER. . lzcntw %ax, %bx
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# CHECK-NEXT: [2,0] D==eER . lzcntw %ax, %bx
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# CHECK-NEXT: [3,0] D===eER . lzcntw %ax, %bx
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# CHECK-NEXT: [4,0] .D===eER . lzcntw %ax, %bx
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# CHECK-NEXT: [5,0] .D====eER . lzcntw %ax, %bx
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# CHECK-NEXT: [6,0] .D=====eER. lzcntw %ax, %bx
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# CHECK-NEXT: [7,0] .D======eER lzcntw %ax, %bx
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 8 4.0 0.1 0.0 lzcntw %ax, %bx

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