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[RISCV] Merge GPRPair and GPRF64Pair (llvm#116094)
As suggested by Craig, this tries to merge the two sets of register classes created in llvm#112983, GPRPair* and GPRF64Pair*. - I added some explicit annotations to `RISCVInstrInfoD.td` which fixed the type inference issues I was seeing from tablegen for select patterns. - I've had to make the behaviour of `splitValueIntoRegisterParts` and `joinRegisterPartsIntoValue` cover more cases, because you cannot bitcast to/from untyped (the bitcast would otherwise have been inserted automatically by TargetLowering code). - I apparently didn't need to change `getNumRegisters` again, which continues to tell me there's a bug in the code for tied inputs. I added some more test coverage of this case but it didn't seem to help find the asserts I was finding before - I think the difference is between the default behaviour for integers which doesn't apply to floats. - There's still a difference between BuildGPRPair and BuildPairF64 (and the same for SplitGPRPair and SplitF64). I'm not happy with this, I think it's quite confusing, as they're very similar, just differing in whether they give a `untyped` or a `f64`. I haven't really worked out how the DAGCombiner copes if one meets the other, I know we have some of this for the f64 variants already, but they're a lot more complex than the GPRPair variants anyway.
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6 files changed

+90
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lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -497,16 +497,10 @@ struct RISCVOperand final : public MCParsedAsmOperand {
497497
RISCVMCRegisterClasses[RISCV::GPRF32RegClassID].contains(Reg.RegNum);
498498
}
499499

500-
bool isGPRF64Pair() const {
501-
return Kind == KindTy::Register &&
502-
RISCVMCRegisterClasses[RISCV::GPRF64PairRegClassID].contains(
503-
Reg.RegNum);
504-
}
505-
506500
bool isGPRAsFPR() const { return isGPR() && Reg.IsGPRAsFPR; }
507501
bool isGPRAsFPR16() const { return isGPRF16() && Reg.IsGPRAsFPR; }
508502
bool isGPRAsFPR32() const { return isGPRF32() && Reg.IsGPRAsFPR; }
509-
bool isGPRPairAsFPR64() const { return isGPRF64Pair() && Reg.IsGPRAsFPR; }
503+
bool isGPRPairAsFPR64() const { return isGPRPair() && Reg.IsGPRAsFPR; }
510504

511505
static bool evaluateConstantImm(const MCExpr *Expr, int64_t &Imm,
512506
RISCVMCExpr::VariantKind &VK) {
@@ -2405,7 +2399,7 @@ ParseStatus RISCVAsmParser::parseGPRPairAsFPR64(OperandVector &Operands) {
24052399
const MCRegisterInfo *RI = getContext().getRegisterInfo();
24062400
MCRegister Pair = RI->getMatchingSuperReg(
24072401
Reg, RISCV::sub_gpr_even,
2408-
&RISCVMCRegisterClasses[RISCV::GPRF64PairRegClassID]);
2402+
&RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
24092403
Operands.push_back(RISCVOperand::createReg(Pair, S, E, /*isGPRAsFPR=*/true));
24102404
return ParseStatus::Success;
24112405
}

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -958,20 +958,14 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
958958
assert((!Subtarget->is64Bit() || Opcode == RISCVISD::BuildGPRPair) &&
959959
"BuildPairF64 only handled here on rv32i_zdinx");
960960

961-
int RegClassID = (Opcode == RISCVISD::BuildGPRPair)
962-
? RISCV::GPRPairRegClassID
963-
: RISCV::GPRF64PairRegClassID;
964-
MVT OutType = (Opcode == RISCVISD::BuildGPRPair) ? MVT::Untyped : MVT::f64;
965-
966961
SDValue Ops[] = {
967-
CurDAG->getTargetConstant(RegClassID, DL, MVT::i32),
962+
CurDAG->getTargetConstant(RISCV::GPRPairRegClassID, DL, MVT::i32),
968963
Node->getOperand(0),
969964
CurDAG->getTargetConstant(RISCV::sub_gpr_even, DL, MVT::i32),
970965
Node->getOperand(1),
971966
CurDAG->getTargetConstant(RISCV::sub_gpr_odd, DL, MVT::i32)};
972967

973-
SDNode *N =
974-
CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, OutType, Ops);
968+
SDNode *N = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, VT, Ops);
975969
ReplaceNode(Node, N);
976970
return;
977971
}
@@ -982,14 +976,15 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
982976
"SplitF64 only handled here on rv32i_zdinx");
983977

984978
if (!SDValue(Node, 0).use_empty()) {
985-
SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL, VT,
979+
SDValue Lo = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_even, DL,
980+
Node->getValueType(0),
986981
Node->getOperand(0));
987982
ReplaceUses(SDValue(Node, 0), Lo);
988983
}
989984

990985
if (!SDValue(Node, 1).use_empty()) {
991-
SDValue Hi = CurDAG->getTargetExtractSubreg(RISCV::sub_gpr_odd, DL, VT,
992-
Node->getOperand(0));
986+
SDValue Hi = CurDAG->getTargetExtractSubreg(
987+
RISCV::sub_gpr_odd, DL, Node->getValueType(1), Node->getOperand(0));
993988
ReplaceUses(SDValue(Node, 1), Hi);
994989
}
995990

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 34 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
133133
if (Subtarget.is64Bit())
134134
addRegisterClass(MVT::f64, &RISCV::GPRRegClass);
135135
else
136-
addRegisterClass(MVT::f64, &RISCV::GPRF64PairRegClass);
136+
addRegisterClass(MVT::f64, &RISCV::GPRPairRegClass);
137137
}
138138

139139
static const MVT::SimpleValueType BoolVecVTs[] = {
@@ -20507,7 +20507,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2050720507
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
2050820508
return std::make_pair(0U, &RISCV::GPRF32NoX0RegClass);
2050920509
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
20510-
return std::make_pair(0U, &RISCV::GPRF64PairNoX0RegClass);
20510+
return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
2051120511
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
2051220512
case 'f':
2051320513
if (VT == MVT::f16) {
@@ -20524,14 +20524,14 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2052420524
if (Subtarget.hasStdExtD())
2052520525
return std::make_pair(0U, &RISCV::FPR64RegClass);
2052620526
if (Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
20527-
return std::make_pair(0U, &RISCV::GPRF64PairNoX0RegClass);
20527+
return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
2052820528
if (Subtarget.hasStdExtZdinx() && Subtarget.is64Bit())
2052920529
return std::make_pair(0U, &RISCV::GPRNoX0RegClass);
2053020530
}
2053120531
break;
2053220532
case 'R':
2053320533
if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
20534-
return std::make_pair(0U, &RISCV::GPRF64PairNoX0RegClass);
20534+
return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
2053520535
return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
2053620536
default:
2053720537
break;
@@ -20570,7 +20570,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2057020570
if (VT == MVT::f32 && Subtarget.hasStdExtZfinx())
2057120571
return std::make_pair(0U, &RISCV::GPRF32CRegClass);
2057220572
if (VT == MVT::f64 && Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
20573-
return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
20573+
return std::make_pair(0U, &RISCV::GPRPairCRegClass);
2057420574
if (!VT.isVector())
2057520575
return std::make_pair(0U, &RISCV::GPRCRegClass);
2057620576
} else if (Constraint == "cf") {
@@ -20588,7 +20588,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2058820588
if (Subtarget.hasStdExtD())
2058920589
return std::make_pair(0U, &RISCV::FPR64CRegClass);
2059020590
if (Subtarget.hasStdExtZdinx() && !Subtarget.is64Bit())
20591-
return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
20591+
return std::make_pair(0U, &RISCV::GPRPairCRegClass);
2059220592
if (Subtarget.hasStdExtZdinx() && Subtarget.is64Bit())
2059320593
return std::make_pair(0U, &RISCV::GPRCRegClass);
2059420594
}
@@ -20752,7 +20752,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2075220752
// Subtarget into account.
2075320753
if (Res.second == &RISCV::GPRF16RegClass ||
2075420754
Res.second == &RISCV::GPRF32RegClass ||
20755-
Res.second == &RISCV::GPRF64PairRegClass)
20755+
Res.second == &RISCV::GPRPairRegClass)
2075620756
return std::make_pair(Res.first, &RISCV::GPRRegClass);
2075720757

2075820758
return Res;
@@ -21379,12 +21379,19 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
2137921379
bool IsABIRegCopy = CC.has_value();
2138021380
EVT ValueVT = Val.getValueType();
2138121381

21382-
if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
21382+
MVT PairVT = Subtarget.is64Bit() ? MVT::i128 : MVT::i64;
21383+
if ((ValueVT == PairVT ||
21384+
(!Subtarget.is64Bit() && Subtarget.hasStdExtZdinx() &&
21385+
ValueVT == MVT::f64)) &&
2138321386
NumParts == 1 && PartVT == MVT::Untyped) {
21384-
// Pairs in Inline Assembly
21387+
// Pairs in Inline Assembly, f64 in Inline assembly on rv32_zdinx
2138521388
MVT XLenVT = Subtarget.getXLenVT();
21389+
if (ValueVT == MVT::f64)
21390+
Val = DAG.getBitcast(MVT::i64, Val);
2138621391
auto [Lo, Hi] = DAG.SplitScalar(Val, DL, XLenVT, XLenVT);
21387-
Parts[0] = DAG.getNode(RISCVISD::BuildGPRPair, DL, MVT::Untyped, Lo, Hi);
21392+
// Always creating an MVT::Untyped part, so always use
21393+
// RISCVISD::BuildGPRPair.
21394+
Parts[0] = DAG.getNode(RISCVISD::BuildGPRPair, DL, PartVT, Lo, Hi);
2138821395
return true;
2138921396
}
2139021397

@@ -21396,7 +21403,7 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
2139621403
Val = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Val);
2139721404
Val = DAG.getNode(ISD::OR, DL, MVT::i32, Val,
2139821405
DAG.getConstant(0xFFFF0000, DL, MVT::i32));
21399-
Val = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Val);
21406+
Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val);
2140021407
Parts[0] = Val;
2140121408
return true;
2140221409
}
@@ -21465,14 +21472,24 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
2146521472
MVT PartVT, EVT ValueVT, std::optional<CallingConv::ID> CC) const {
2146621473
bool IsABIRegCopy = CC.has_value();
2146721474

21468-
if (ValueVT == (Subtarget.is64Bit() ? MVT::i128 : MVT::i64) &&
21475+
MVT PairVT = Subtarget.is64Bit() ? MVT::i128 : MVT::i64;
21476+
if ((ValueVT == PairVT ||
21477+
(!Subtarget.is64Bit() && Subtarget.hasStdExtZdinx() &&
21478+
ValueVT == MVT::f64)) &&
2146921479
NumParts == 1 && PartVT == MVT::Untyped) {
21470-
// Pairs in Inline Assembly
21480+
// Pairs in Inline Assembly, f64 in Inline assembly on rv32_zdinx
2147121481
MVT XLenVT = Subtarget.getXLenVT();
21472-
SDValue Res = DAG.getNode(RISCVISD::SplitGPRPair, DL,
21473-
DAG.getVTList(XLenVT, XLenVT), Parts[0]);
21474-
return DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Res.getValue(0),
21475-
Res.getValue(1));
21482+
21483+
SDValue Val = Parts[0];
21484+
// Always starting with an MVT::Untyped part, so always use
21485+
// RISCVISD::SplitGPRPair
21486+
Val = DAG.getNode(RISCVISD::SplitGPRPair, DL, DAG.getVTList(XLenVT, XLenVT),
21487+
Val);
21488+
Val = DAG.getNode(ISD::BUILD_PAIR, DL, PairVT, Val.getValue(0),
21489+
Val.getValue(1));
21490+
if (ValueVT == MVT::f64)
21491+
Val = DAG.getBitcast(ValueVT, Val);
21492+
return Val;
2147621493
}
2147721494

2147821495
if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@ def FPR64INX : RegisterOperand<GPR> {
5252
let DecoderMethod = "DecodeGPRRegisterClass";
5353
}
5454

55-
def FPR64IN32X : RegisterOperand<GPRF64Pair> {
55+
def FPR64IN32X : RegisterOperand<GPRPair> {
5656
let ParserMatchClass = GPRPairAsFPR;
5757
}
5858

@@ -457,16 +457,16 @@ def : PatSetCC<FPR64INX, any_fsetccs, SETOLE, FLE_D_INX, f64>;
457457

458458
let Predicates = [HasStdExtZdinx, IsRV32] in {
459459
// Match signaling FEQ_D
460-
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETEQ)),
460+
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs2, SETEQ)),
461461
(AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
462462
(XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
463-
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs2, SETOEQ)),
463+
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs2, SETOEQ)),
464464
(AND (XLenVT (FLE_D_IN32X $rs1, $rs2)),
465465
(XLenVT (FLE_D_IN32X $rs2, $rs1)))>;
466466
// If both operands are the same, use a single FLE.
467-
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETEQ)),
467+
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs1, SETEQ)),
468468
(FLE_D_IN32X $rs1, $rs1)>;
469-
def : Pat<(XLenVT (strict_fsetccs FPR64IN32X:$rs1, FPR64IN32X:$rs1, SETOEQ)),
469+
def : Pat<(XLenVT (strict_fsetccs (f64 FPR64IN32X:$rs1), FPR64IN32X:$rs1, SETOEQ)),
470470
(FLE_D_IN32X $rs1, $rs1)>;
471471

472472
def : PatSetCC<FPR64IN32X, any_fsetccs, SETLT, FLT_D_IN32X, f64>;
@@ -523,15 +523,15 @@ def PseudoFROUND_D_IN32X : PseudoFROUND<FPR64IN32X, f64>;
523523

524524
/// Loads
525525
let isCall = 0, mayLoad = 1, mayStore = 0, Size = 8, isCodeGenOnly = 1 in
526-
def PseudoRV32ZdinxLD : Pseudo<(outs GPRF64Pair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
526+
def PseudoRV32ZdinxLD : Pseudo<(outs GPRPair:$dst), (ins GPR:$rs1, simm12:$imm12), []>;
527527
def : Pat<(f64 (load (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12))),
528528
(PseudoRV32ZdinxLD GPR:$rs1, simm12:$imm12)>;
529529

530530
/// Stores
531531
let isCall = 0, mayLoad = 0, mayStore = 1, Size = 8, isCodeGenOnly = 1 in
532-
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRF64Pair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
533-
def : Pat<(store (f64 GPRF64Pair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
534-
(PseudoRV32ZdinxSD GPRF64Pair:$rs2, GPR:$rs1, simm12:$imm12)>;
532+
def PseudoRV32ZdinxSD : Pseudo<(outs), (ins GPRPair:$rs2, GPRNoX0:$rs1, simm12:$imm12), []>;
533+
def : Pat<(store (f64 GPRPair:$rs2), (AddrRegImmINX (XLenVT GPR:$rs1), simm12:$imm12)),
534+
(PseudoRV32ZdinxSD GPRPair:$rs2, GPR:$rs1, simm12:$imm12)>;
535535
} // Predicates = [HasStdExtZdinx, IsRV32]
536536

537537
let Predicates = [HasStdExtD, IsRV32] in {

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.td‎

Lines changed: 3 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -325,7 +325,7 @@ let RegAltNameIndices = [ABIRegAltName] in {
325325

326326
let RegInfos = XLenPairRI,
327327
DecoderMethod = "DecodeGPRPairRegisterClass" in {
328-
def GPRPair : RISCVRegisterClass<[XLenPairVT], 64, (add
328+
def GPRPair : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
329329
X10_X11, X12_X13, X14_X15, X16_X17,
330330
X6_X7,
331331
X28_X29, X30_X31,
@@ -334,11 +334,11 @@ def GPRPair : RISCVRegisterClass<[XLenPairVT], 64, (add
334334
X0_Pair, X2_X3, X4_X5
335335
)>;
336336

337-
def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT], 64, (sub GPRPair, X0_Pair)>;
337+
def GPRPairNoX0 : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (sub GPRPair, X0_Pair)>;
338338
} // let RegInfos = XLenPairRI, DecoderMethod = "DecodeGPRPairRegisterClass"
339339

340340
let RegInfos = XLenPairRI in
341-
def GPRPairC : RISCVRegisterClass<[XLenPairVT], 64, (add
341+
def GPRPairC : RISCVRegisterClass<[XLenPairVT, XLenPairFVT], 64, (add
342342
X10_X11, X12_X13, X14_X15, X8_X9
343343
)>;
344344

@@ -464,22 +464,6 @@ def GPRF32C : RISCVRegisterClass<[f32], 32, (add (sequence "X%u_W", 10, 15),
464464
(sequence "X%u_W", 8, 9))>;
465465
def GPRF32NoX0 : RISCVRegisterClass<[f32], 32, (sub GPRF32, X0_W)>;
466466

467-
let DecoderMethod = "DecodeGPRPairRegisterClass" in
468-
def GPRF64Pair : RISCVRegisterClass<[XLenPairFVT], 64, (add
469-
X10_X11, X12_X13, X14_X15, X16_X17,
470-
X6_X7,
471-
X28_X29, X30_X31,
472-
X8_X9,
473-
X18_X19, X20_X21, X22_X23, X24_X25, X26_X27,
474-
X0_Pair, X2_X3, X4_X5
475-
)>;
476-
477-
def GPRF64PairC : RISCVRegisterClass<[XLenPairFVT], 64, (add
478-
X10_X11, X12_X13, X14_X15, X8_X9
479-
)>;
480-
481-
def GPRF64PairNoX0 : RISCVRegisterClass<[XLenPairFVT], 64, (sub GPRF64Pair, X0_Pair)>;
482-
483467
//===----------------------------------------------------------------------===//
484468
// Vector type mapping to LLVM types.
485469
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/zdinx-asm-constraint.ll‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,42 @@ entry:
4646
ret void
4747
}
4848

49+
define dso_local void @zdinx_asm_inout(ptr nocapture noundef writeonly %a, double noundef %b) nounwind {
50+
; CHECK-LABEL: zdinx_asm_inout:
51+
; CHECK: # %bb.0: # %entry
52+
; CHECK-NEXT: mv a3, a2
53+
; CHECK-NEXT: mv a2, a1
54+
; CHECK-NEXT: #APP
55+
; CHECK-NEXT: fmv.d a2, a2
56+
; CHECK-NEXT: #NO_APP
57+
; CHECK-NEXT: sw a2, 8(a0)
58+
; CHECK-NEXT: sw a3, 12(a0)
59+
; CHECK-NEXT: ret
60+
entry:
61+
%arrayidx = getelementptr inbounds double, ptr %a, i32 1
62+
%0 = tail call double asm "fsgnj.d $0, $1, $1", "=r,0"(double %b)
63+
store double %0, ptr %arrayidx, align 8
64+
ret void
65+
}
66+
67+
define dso_local void @zdinx_asm_Pr_inout(ptr nocapture noundef writeonly %a, double noundef %b) nounwind {
68+
; CHECK-LABEL: zdinx_asm_Pr_inout:
69+
; CHECK: # %bb.0: # %entry
70+
; CHECK-NEXT: mv a3, a2
71+
; CHECK-NEXT: mv a2, a1
72+
; CHECK-NEXT: #APP
73+
; CHECK-NEXT: fabs.d a2, a2
74+
; CHECK-NEXT: #NO_APP
75+
; CHECK-NEXT: sw a2, 8(a0)
76+
; CHECK-NEXT: sw a3, 12(a0)
77+
; CHECK-NEXT: ret
78+
entry:
79+
%arrayidx = getelementptr inbounds double, ptr %a, i32 1
80+
%0 = tail call double asm "fsgnjx.d $0, $1, $1", "=R,0"(double %b)
81+
store double %0, ptr %arrayidx, align 8
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ret void
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}
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define dso_local void @zfinx_asm(ptr nocapture noundef writeonly %a, float noundef %b, float noundef %c) nounwind {
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; CHECK-LABEL: zfinx_asm:
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; CHECK: # %bb.0: # %entry

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