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[llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.
This patch makes it so that cases where multiple instructions that differ only in their FrameIndex MachineOperand values no longer collide. For instance: %1:_(p0) = G_FRAME_INDEX %stack.0 %2:_(p0) = G_FRAME_INDEX %stack.1 Prior to this patch these instructions would collide together. Differential Revision: https://reviews.llvm.org/D71583
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llvm/lib/CodeGen/MIRVRegNamerUtils.cpp

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@@ -68,6 +68,8 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
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return MO.getImm();
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case MachineOperand::MO_TargetIndex:
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return MO.getOffset() | (MO.getTargetFlags() << 16);
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case MachineOperand::MO_FrameIndex:
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return llvm::hash_value(MO);
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// We could explicitly handle all the types of the MachineOperand,
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// here but we can just return a common number until we find a
@@ -77,7 +79,6 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
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// TODO: Handle the following Index/ID/Predicate cases. They can
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// be hashed on in a stable manner.
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case MachineOperand::MO_FrameIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_JumpTableIndex:
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case MachineOperand::MO_CFIIndex:
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@@ -0,0 +1,23 @@
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# RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: f
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stack:
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- { id: 0, size: 4 }
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- { id: 1, size: 4 }
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fixedStack:
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- { id: 0, offset: 0, size: 4 }
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- { id: 1, offset: 0, size: 4 }
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body: |
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bb.1:
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; CHECK: _1:_(p0) = G_FRAME_INDEX %stack.{{[0-1]}}
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; CHECK: _1:_(p0) = G_FRAME_INDEX %stack.{{[0-1]}}
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; CHECK: _1:gr32 = MOV32rm %fixed-stack.{{[0-1]}}
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; CHECK: _1:gr32 = MOV32rm %fixed-stack.{{[0-1]}}
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%1:_(p0) = G_FRAME_INDEX %stack.0
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%2:_(p0) = G_FRAME_INDEX %stack.1
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%3:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _
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%4:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _
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...

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