[RISCV] Add IsRV32 to the isel pattern for ZIP_RV32/UNZIP_RV32. NFC

I think the i32 in the pattern prevents this from matching on RV64,
but using IsRV32 is safer.

Add tests for RV64 to make sure we don't print zip or unzip
because we incorrectly picked ZIP_RV32/UNZIP_RV32.

Author: topperc

llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

@@ -852,7 +852,9 @@ let Predicates = [HasStdExtZbpOrZbkb] in {
 // We treat brev8 as a separate instruction, so match it directly. We also
 // use this for brev8 when lowering bitreverse with Zbkb.
 def : Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1)>;
+}
 
+let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in {
 // We treat zip and unzip as separate instructions, so match it directly.
 def : Pat<(i32 (riscv_shfl GPR:$rs1, 15)), (ZIP_RV32 GPR:$rs1)>;
 def : Pat<(i32 (riscv_unshfl GPR:$rs1, 15)), (UNZIP_RV32 GPR:$rs1)>;

llvm/test/CodeGen/RISCV/rv64zbp-intrinsic.ll

@@ -100,6 +100,15 @@ define signext i32 @shfli32(i32 signext %a) nounwind {
  ret i32 %tmp
 }
 
+define signext i32 @zip_w(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: zip_w:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    zip.w a0, a0
+; RV64ZBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.shfl.i32(i32 %a, i32 15)
+ ret i32 %tmp
+}
+
 declare i32 @llvm.riscv.unshfl.i32(i32 %a, i32 %b)
 
 define signext i32 @unshfl32(i32 signext %a, i32 signext %b) nounwind {
@@ -132,6 +141,15 @@ define signext i32 @unshfli32(i32 signext %a) nounwind {
  ret i32 %tmp
 }
 
+define signext i32 @unzip_w(i32 signext %a) nounwind {
+; RV64ZBP-LABEL: unzip_w:
+; RV64ZBP:       # %bb.0:
+; RV64ZBP-NEXT:    unzip.w a0, a0
+; RV64ZBP-NEXT:    ret
+  %tmp = call i32 @llvm.riscv.unshfl.i32(i32 %a, i32 15)
+ ret i32 %tmp
+}
+
 declare i64 @llvm.riscv.grev.i64(i64 %a, i64 %b)
 
 define i64 @grev64(i64 %a, i64 %b) nounwind {