@@ -338,29 +338,6 @@ class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
338338 opcodestr, "$vd, $vs2$vm">;
339339} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
340340
341- let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
342- // vamo vd, (rs1), vs2, vd, vm
343- class VAMOWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
344- : RVInstVAMO<amoop, width.Value{2-0}, (outs VR:$vd_wd),
345- (ins GPR:$rs1, VR:$vs2, VR:$vd, VMaskOp:$vm),
346- opcodestr, "$vd_wd, (${rs1}), $vs2, $vd$vm"> {
347- let Constraints = "$vd_wd = $vd";
348- let wd = 1;
349- bits<5> vd;
350- let Inst{11-7} = vd;
351- }
352-
353- // vamo x0, (rs1), vs2, vs3, vm
354- class VAMONoWd<RISCVAMOOP amoop, RISCVWidth width, string opcodestr>
355- : RVInstVAMO<amoop, width.Value{2-0}, (outs),
356- (ins GPR:$rs1, VR:$vs2, VR:$vs3, VMaskOp:$vm),
357- opcodestr, "x0, (${rs1}), $vs2, $vs3$vm"> {
358- bits<5> vs3;
359- let Inst{11-7} = vs3;
360- }
361-
362- } // hasSideEffects = 0, mayLoad = 1, mayStore = 1
363-
364341//===----------------------------------------------------------------------===//
365342// Combination of instruction classes.
366343// Use these multiclasses to define instructions more easily.
@@ -779,11 +756,6 @@ multiclass VCPR_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
779756 Sched<[WriteVCompressV, ReadVCompressV, ReadVCompressV]>;
780757}
781758
782- multiclass VAMO<RISCVAMOOP amoop, RISCVWidth width, string opcodestr> {
783- def _WD : VAMOWd<amoop, width, opcodestr>;
784- def _UNWD : VAMONoWd<amoop, width, opcodestr>;
785- }
786-
787759multiclass VWholeLoadN<bits<3> nf, string opcodestr, RegisterClass VRC> {
788760 foreach l = [8, 16, 32, 64] in {
789761 defvar w = !cast<RISCVWidth>("LSWidth" # l);
@@ -822,7 +794,7 @@ foreach eew = [8, 16, 32, 64] in {
822794 // Vector Strided Instructions
823795 def VLSE#eew#_V : VStridedLoad<w, "vlse"#eew#".v">, VLSSched<eew>;
824796 def VSSE#eew#_V : VStridedStore<w, "vsse"#eew#".v">, VSSSched<eew>;
825-
797+
826798 // Vector Indexed Instructions
827799 def VLUXEI#eew#_V :
828800 VIndexedLoad<MOPLDIndexedUnord, w, "vluxei"#eew#".v">, VLXSched<eew, "U">;
@@ -1469,31 +1441,4 @@ let Predicates = [HasStdExtZvlsseg] in {
14691441 }
14701442} // Predicates = [HasStdExtZvlsseg]
14711443
1472- let Predicates = [HasStdExtZvamo, HasStdExtA] in {
1473- foreach eew = [8, 16, 32] in {
1474- defvar w = !cast<RISCVWidth>("LSWidth"#eew);
1475- defm VAMOSWAPEI#eew : VAMO<AMOOPVamoSwap, w, "vamoswapei"#eew#".v">;
1476- defm VAMOADDEI#eew : VAMO<AMOOPVamoAdd, w, "vamoaddei"#eew#".v">;
1477- defm VAMOXOREI#eew : VAMO<AMOOPVamoXor, w, "vamoxorei"#eew#".v">;
1478- defm VAMOANDEI#eew : VAMO<AMOOPVamoAnd, w, "vamoandei"#eew#".v">;
1479- defm VAMOOREI#eew : VAMO<AMOOPVamoOr, w, "vamoorei"#eew#".v">;
1480- defm VAMOMINEI#eew : VAMO<AMOOPVamoMin, w, "vamominei"#eew#".v">;
1481- defm VAMOMAXEI#eew : VAMO<AMOOPVamoMax, w, "vamomaxei"#eew#".v">;
1482- defm VAMOMINUEI#eew : VAMO<AMOOPVamoMinu, w, "vamominuei"#eew#".v">;
1483- defm VAMOMAXUEI#eew : VAMO<AMOOPVamoMaxu, w, "vamomaxuei"#eew#".v">;
1484- }
1485- } // Predicates = [HasStdExtZvamo, HasStdExtA]
1486-
1487- let Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64] in {
1488- defm VAMOSWAPEI64 : VAMO<AMOOPVamoSwap, LSWidth64, "vamoswapei64.v">;
1489- defm VAMOADDEI64 : VAMO<AMOOPVamoAdd, LSWidth64, "vamoaddei64.v">;
1490- defm VAMOXOREI64 : VAMO<AMOOPVamoXor, LSWidth64, "vamoxorei64.v">;
1491- defm VAMOANDEI64 : VAMO<AMOOPVamoAnd, LSWidth64, "vamoandei64.v">;
1492- defm VAMOOREI64 : VAMO<AMOOPVamoOr, LSWidth64, "vamoorei64.v">;
1493- defm VAMOMINEI64 : VAMO<AMOOPVamoMin, LSWidth64, "vamominei64.v">;
1494- defm VAMOMAXEI64 : VAMO<AMOOPVamoMax, LSWidth64, "vamomaxei64.v">;
1495- defm VAMOMINUEI64 : VAMO<AMOOPVamoMinu, LSWidth64, "vamominuei64.v">;
1496- defm VAMOMAXUEI64 : VAMO<AMOOPVamoMaxu, LSWidth64, "vamomaxuei64.v">;
1497- } // Predicates = [HasStdExtZvamo, HasStdExtA, IsRV64]
1498-
14991444include "RISCVInstrInfoVPseudos.td"
0 commit comments