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[AArch64][SME2] Add Multi-vector add vector intrinsics
Add the following intrinsic: ADD vectors NOTE: These intrinsics are still in development and are subject to future changes. Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D142455
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‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

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Original file line numberDiff line numberDiff line change
@@ -3132,4 +3132,10 @@ let TargetPrefix = "aarch64" in {
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def int_aarch64_sme_write_vg1x2 : SME2_ZA_ArrayVector_Write_VG2_Intrinsic;
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def int_aarch64_sme_write_vg1x4 : SME2_ZA_ArrayVector_Write_VG4_Intrinsic;
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//
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// Multi-Single Vector add
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//
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def int_aarch64_sve_add_single_x2 : SME2_VG2_Multi_Single_Intrinsic;
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def int_aarch64_sve_add_single_x4 : SME2_VG4_Multi_Single_Intrinsic;
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}

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp‎

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Original file line numberDiff line numberDiff line change
@@ -5061,6 +5061,20 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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AArch64::FCLAMP_VG4_4Z4Z_D}))
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SelectClamp(Node, 4, Op);
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return;
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case Intrinsic::aarch64_sve_add_single_x2:
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if (auto Op = SelectOpcodeFromVT<SelectTypeKind::Int>(
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Node->getValueType(0),
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{AArch64::ADD_VG2_2ZZ_B, AArch64::ADD_VG2_2ZZ_H,
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AArch64::ADD_VG2_2ZZ_S, AArch64::ADD_VG2_2ZZ_D}))
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SelectDestructiveMultiIntrinsic(Node, 2, false, Op);
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return;
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case Intrinsic::aarch64_sve_add_single_x4:
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if (auto Op = SelectOpcodeFromVT<SelectTypeKind::Int>(
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Node->getValueType(0),
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{AArch64::ADD_VG4_4ZZ_B, AArch64::ADD_VG4_4ZZ_H,
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AArch64::ADD_VG4_4ZZ_S, AArch64::ADD_VG4_4ZZ_D}))
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SelectDestructiveMultiIntrinsic(Node, 4, false, Op);
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return;
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}
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break;
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}

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-add.ll‎

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Original file line numberDiff line numberDiff line change
@@ -370,6 +370,153 @@ define void @multi_vector_add_za_vg1x4_f64(i32 %slice, <vscale x 2 x double> %zn
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ret void
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}
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;
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; ADD Vectors Multi-Single x2
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;
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define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: multi_vec_add_single_x2_s8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: add { z4.b, z5.b }, { z4.b, z5.b }, z3.b
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 16 x i8>, <vscale x 16 x i8> }
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@llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2,
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<vscale x 16 x i8> %zm)
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ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res
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}
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define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_single_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {
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; CHECK-LABEL: multi_vec_add_single_x2_s16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: add { z4.h, z5.h }, { z4.h, z5.h }, z3.h
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x i16>, <vscale x 8 x i16> }
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@llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2,
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<vscale x 8 x i16> %zm)
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ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res
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}
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define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_single_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {
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; CHECK-LABEL: multi_vec_add_single_x2_s32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: add { z4.s, z5.s }, { z4.s, z5.s }, z3.s
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x i32>, <vscale x 4 x i32> }
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@llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2,
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<vscale x 4 x i32> %zm)
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ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res
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}
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define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {
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; CHECK-LABEL: multi_vec_add_single_x2_s64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: add { z4.d, z5.d }, { z4.d, z5.d }, z3.d
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x i64>, <vscale x 2 x i64> }
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@llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2,
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<vscale x 2 x i64> %zm)
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ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
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}
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;
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; ADD Vectors Multi-Single x4
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;
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define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_add_single_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8>%zm) {
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; CHECK-LABEL: multi_vec_add_single_x4_s8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z27.d, z4.d
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; CHECK-NEXT: mov z26.d, z3.d
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: add { z24.b - z27.b }, { z24.b - z27.b }, z5.b
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z26.d
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; CHECK-NEXT: mov z3.d, z27.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }
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@llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2,
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<vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,
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<vscale x 16 x i8> %zm)
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ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res
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}
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define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_add_x4_single_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {
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; CHECK-LABEL: multi_vec_add_x4_single_s16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z27.d, z4.d
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; CHECK-NEXT: mov z26.d, z3.d
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: add { z24.h - z27.h }, { z24.h - z27.h }, z5.h
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z26.d
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; CHECK-NEXT: mov z3.d, z27.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }
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@llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2,
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<vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,
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<vscale x 8 x i16> %zm)
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ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res
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}
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define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_add_x4_single_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {
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; CHECK-LABEL: multi_vec_add_x4_single_s32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z27.d, z4.d
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; CHECK-NEXT: mov z26.d, z3.d
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: add { z24.s - z27.s }, { z24.s - z27.s }, z5.s
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z26.d
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; CHECK-NEXT: mov z3.d, z27.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }
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@llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2,
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<vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,
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<vscale x 4 x i32> %zm)
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ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res
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}
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define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_add_x4_single_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {
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; CHECK-LABEL: multi_vec_add_x4_single_s64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z27.d, z4.d
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; CHECK-NEXT: mov z26.d, z3.d
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: add { z24.d - z27.d }, { z24.d - z27.d }, z5.d
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; CHECK-NEXT: mov z0.d, z24.d
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; CHECK-NEXT: mov z1.d, z25.d
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; CHECK-NEXT: mov z2.d, z26.d
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; CHECK-NEXT: mov z3.d, z27.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
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@llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2,
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<vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,
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<vscale x 2 x i64> %zm)
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ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
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}
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declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare void@llvm.aarch64.sme.add.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare void@llvm.aarch64.sme.add.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
@@ -386,3 +533,11 @@ declare [email protected](i32, <vscale x 4 x float>,
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declare void@llvm.aarch64.sme.add.za64.vg1x2.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>)
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declare void@llvm.aarch64.sme.add.za32.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>)
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declare void@llvm.aarch64.sme.add.za64.vg1x4.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>)
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declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.add.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.add.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.add.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.add.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)

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