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[NFC][asan] Replace AsanInited/ENSURE_ASAN_INITED with TryAsanInitFromRtl (llvm#74172)
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5 files changed

+43
-44
lines changed

5 files changed

+43
-44
lines changed

‎compiler-rt/lib/asan/asan_interceptors.cpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -558,9 +558,8 @@ INTERCEPTOR(char *, strcpy, char *to, const char *from) {
558558
INTERCEPTOR(char*, strdup, const char *s) {
559559
void *ctx;
560560
ASAN_INTERCEPTOR_ENTER(ctx, strdup);
561-
if (UNLIKELY(!AsanInited()))
561+
if (UNLIKELY(!TryAsanInitFromRtl()))
562562
return internal_strdup(s);
563-
ENSURE_ASAN_INITED();
564563
uptr length = internal_strlen(s);
565564
if (flags()->replace_str) {
566565
ASAN_READ_RANGE(ctx, s, length + 1);
@@ -577,9 +576,8 @@ INTERCEPTOR(char*, strdup, const char *s) {
577576
INTERCEPTOR(char*, __strdup, const char *s) {
578577
void *ctx;
579578
ASAN_INTERCEPTOR_ENTER(ctx, strdup);
580-
if (UNLIKELY(!AsanInited()))
579+
if (UNLIKELY(!TryAsanInitFromRtl()))
581580
return internal_strdup(s);
582-
ENSURE_ASAN_INITED();
583581
uptr length = internal_strlen(s);
584582
if (flags()->replace_str) {
585583
ASAN_READ_RANGE(ctx, s, length + 1);

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21006,18 +21006,20 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
2100621006
&IsFast) ||
2100721007
!IsFast)
2100821008
return SDValue();
21009+
EVT PtrVT = Ptr.getValueType();
2100921010

21011+
SDValue Offset =
21012+
DAG.getNode(ISD::MUL, DL, PtrVT, DAG.getZExtOrTrunc(Idx, DL, PtrVT),
21013+
DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
21014+
SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset);
2101021015
MachinePointerInfo PointerInfo(ST->getAddressSpace());
2101121016

2101221017
// If the offset is a known constant then try to recover the pointer
2101321018
// info
21014-
SDValue NewPtr;
2101521019
if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
2101621020
unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8;
2101721021
NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(COffset), DL);
2101821022
PointerInfo = ST->getPointerInfo().getWithOffset(COffset);
21019-
} else {
21020-
NewPtr = TLI.getVectorElementPointer(DAG, Ptr, Value.getValueType(), Idx);
2102121023
}
2102221024

2102321025
return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(),

‎llvm/test/CodeGen/Mips/msa/basic_operations.ll‎

Lines changed: 4 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1879,7 +1879,6 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
18791879
; O32-NEXT: addu $1, $2, $25
18801880
; O32-NEXT: lw $2, %got(i32)($1)
18811881
; O32-NEXT: lw $2, 0($2)
1882-
; O32-NEXT: andi $2, $2, 15
18831882
; O32-NEXT: lw $1, %got(v16i8)($1)
18841883
; O32-NEXT: addu $1, $1, $2
18851884
; O32-NEXT: jr $ra
@@ -1892,7 +1891,6 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
18921891
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
18931892
; N32-NEXT: lw $2, %got_disp(i32)($1)
18941893
; N32-NEXT: lw $2, 0($2)
1895-
; N32-NEXT: andi $2, $2, 15
18961894
; N32-NEXT: lw $1, %got_disp(v16i8)($1)
18971895
; N32-NEXT: addu $1, $1, $2
18981896
; N32-NEXT: jr $ra
@@ -1904,8 +1902,7 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
19041902
; N64-NEXT: daddu $1, $1, $25
19051903
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
19061904
; N64-NEXT: ld $2, %got_disp(i32)($1)
1907-
; N64-NEXT: lw $2, 0($2)
1908-
; N64-NEXT: andi $2, $2, 15
1905+
; N64-NEXT: lwu $2, 0($2)
19091906
; N64-NEXT: ld $1, %got_disp(v16i8)($1)
19101907
; N64-NEXT: daddu $1, $1, $2
19111908
; N64-NEXT: jr $ra
@@ -1928,7 +1925,6 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19281925
; O32-NEXT: addu $1, $2, $25
19291926
; O32-NEXT: lw $2, %got(i32)($1)
19301927
; O32-NEXT: lw $2, 0($2)
1931-
; O32-NEXT: andi $2, $2, 7
19321928
; O32-NEXT: lw $1, %got(v8i16)($1)
19331929
; O32-NEXT: lsa $1, $2, $1, 1
19341930
; O32-NEXT: jr $ra
@@ -1941,7 +1937,6 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19411937
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
19421938
; N32-NEXT: lw $2, %got_disp(i32)($1)
19431939
; N32-NEXT: lw $2, 0($2)
1944-
; N32-NEXT: andi $2, $2, 7
19451940
; N32-NEXT: lw $1, %got_disp(v8i16)($1)
19461941
; N32-NEXT: lsa $1, $2, $1, 1
19471942
; N32-NEXT: jr $ra
@@ -1953,8 +1948,7 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19531948
; N64-NEXT: daddu $1, $1, $25
19541949
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
19551950
; N64-NEXT: ld $2, %got_disp(i32)($1)
1956-
; N64-NEXT: lw $2, 0($2)
1957-
; N64-NEXT: andi $2, $2, 7
1951+
; N64-NEXT: lwu $2, 0($2)
19581952
; N64-NEXT: ld $1, %got_disp(v8i16)($1)
19591953
; N64-NEXT: dlsa $1, $2, $1, 1
19601954
; N64-NEXT: jr $ra
@@ -1977,7 +1971,6 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
19771971
; O32-NEXT: addu $1, $2, $25
19781972
; O32-NEXT: lw $2, %got(i32)($1)
19791973
; O32-NEXT: lw $2, 0($2)
1980-
; O32-NEXT: andi $2, $2, 3
19811974
; O32-NEXT: lw $1, %got(v4i32)($1)
19821975
; O32-NEXT: lsa $1, $2, $1, 2
19831976
; O32-NEXT: jr $ra
@@ -1990,7 +1983,6 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
19901983
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
19911984
; N32-NEXT: lw $2, %got_disp(i32)($1)
19921985
; N32-NEXT: lw $2, 0($2)
1993-
; N32-NEXT: andi $2, $2, 3
19941986
; N32-NEXT: lw $1, %got_disp(v4i32)($1)
19951987
; N32-NEXT: lsa $1, $2, $1, 2
19961988
; N32-NEXT: jr $ra
@@ -2002,8 +1994,7 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
20021994
; N64-NEXT: daddu $1, $1, $25
20031995
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
20041996
; N64-NEXT: ld $2, %got_disp(i32)($1)
2005-
; N64-NEXT: lw $2, 0($2)
2006-
; N64-NEXT: andi $2, $2, 3
1997+
; N64-NEXT: lwu $2, 0($2)
20071998
; N64-NEXT: ld $1, %got_disp(v4i32)($1)
20081999
; N64-NEXT: dlsa $1, $2, $1, 2
20092000
; N64-NEXT: jr $ra
@@ -2027,7 +2018,6 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20272018
; O32-NEXT: addu $1, $2, $25
20282019
; O32-NEXT: lw $2, %got(i32)($1)
20292020
; O32-NEXT: lw $2, 0($2)
2030-
; O32-NEXT: andi $2, $2, 1
20312021
; O32-NEXT: lw $1, %got(v2i64)($1)
20322022
; O32-NEXT: lsa $1, $2, $1, 3
20332023
; O32-NEXT: sw $5, 4($1)
@@ -2041,7 +2031,6 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20412031
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
20422032
; N32-NEXT: lw $2, %got_disp(i32)($1)
20432033
; N32-NEXT: lw $2, 0($2)
2044-
; N32-NEXT: andi $2, $2, 1
20452034
; N32-NEXT: lw $1, %got_disp(v2i64)($1)
20462035
; N32-NEXT: lsa $1, $2, $1, 3
20472036
; N32-NEXT: jr $ra
@@ -2053,8 +2042,7 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20532042
; N64-NEXT: daddu $1, $1, $25
20542043
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
20552044
; N64-NEXT: ld $2, %got_disp(i32)($1)
2056-
; N64-NEXT: lw $2, 0($2)
2057-
; N64-NEXT: andi $2, $2, 1
2045+
; N64-NEXT: lwu $2, 0($2)
20582046
; N64-NEXT: ld $1, %got_disp(v2i64)($1)
20592047
; N64-NEXT: dlsa $1, $2, $1, 3
20602048
; N64-NEXT: jr $ra

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll‎

Lines changed: 32 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -321,13 +321,20 @@ define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {
321321
}
322322

323323
define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {
324-
; CHECK-LABEL: insertelt_v32i16_store:
325-
; CHECK: # %bb.0:
326-
; CHECK-NEXT: andi a2, a2, 31
327-
; CHECK-NEXT: slli a2, a2, 1
328-
; CHECK-NEXT: add a0, a0, a2
329-
; CHECK-NEXT: sh a1, 0(a0)
330-
; CHECK-NEXT: ret
324+
; RV32-LABEL: insertelt_v32i16_store:
325+
; RV32: # %bb.0:
326+
; RV32-NEXT: slli a2, a2, 1
327+
; RV32-NEXT: add a0, a0, a2
328+
; RV32-NEXT: sh a1, 0(a0)
329+
; RV32-NEXT: ret
330+
;
331+
; RV64-LABEL: insertelt_v32i16_store:
332+
; RV64: # %bb.0:
333+
; RV64-NEXT: slli a2, a2, 32
334+
; RV64-NEXT: srli a2, a2, 31
335+
; RV64-NEXT: add a0, a0, a2
336+
; RV64-NEXT: sh a1, 0(a0)
337+
; RV64-NEXT: ret
331338
%a = load <32 x i16>, ptr %x
332339
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
333340
store <32 x i16> %b, ptr %x
@@ -359,13 +366,20 @@ define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {
359366
}
360367

361368
define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {
362-
; CHECK-LABEL: insertelt_v8f32_store:
363-
; CHECK: # %bb.0:
364-
; CHECK-NEXT: andi a1, a1, 7
365-
; CHECK-NEXT: slli a1, a1, 2
366-
; CHECK-NEXT: add a0, a0, a1
367-
; CHECK-NEXT: fsw fa0, 0(a0)
368-
; CHECK-NEXT: ret
369+
; RV32-LABEL: insertelt_v8f32_store:
370+
; RV32: # %bb.0:
371+
; RV32-NEXT: slli a1, a1, 2
372+
; RV32-NEXT: add a0, a0, a1
373+
; RV32-NEXT: fsw fa0, 0(a0)
374+
; RV32-NEXT: ret
375+
;
376+
; RV64-LABEL: insertelt_v8f32_store:
377+
; RV64: # %bb.0:
378+
; RV64-NEXT: slli a1, a1, 32
379+
; RV64-NEXT: srli a1, a1, 30
380+
; RV64-NEXT: add a0, a0, a1
381+
; RV64-NEXT: fsw fa0, 0(a0)
382+
; RV64-NEXT: ret
369383
%a = load <8 x float>, ptr %x
370384
%b = insertelement <8 x float> %a, float %y, i32 %idx
371385
store <8 x float> %b, ptr %x
@@ -429,7 +443,6 @@ define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {
429443
define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
430444
; RV32-LABEL: insertelt_v8i64_store:
431445
; RV32: # %bb.0:
432-
; RV32-NEXT: andi a1, a1, 7
433446
; RV32-NEXT: slli a1, a1, 3
434447
; RV32-NEXT: add a0, a0, a1
435448
; RV32-NEXT: li a1, -1
@@ -439,8 +452,8 @@ define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
439452
;
440453
; RV64-LABEL: insertelt_v8i64_store:
441454
; RV64: # %bb.0:
442-
; RV64-NEXT: andi a1, a1, 7
443-
; RV64-NEXT: slli a1, a1, 3
455+
; RV64-NEXT: slli a1, a1, 32
456+
; RV64-NEXT: srli a1, a1, 29
444457
; RV64-NEXT: add a0, a0, a1
445458
; RV64-NEXT: li a1, -1
446459
; RV64-NEXT: sd a1, 0(a0)
@@ -508,7 +521,6 @@ define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {
508521
define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
509522
; RV32-LABEL: insertelt_c6_v8i64_store:
510523
; RV32: # %bb.0:
511-
; RV32-NEXT: andi a1, a1, 7
512524
; RV32-NEXT: slli a1, a1, 3
513525
; RV32-NEXT: add a0, a0, a1
514526
; RV32-NEXT: sw zero, 4(a0)
@@ -518,8 +530,8 @@ define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
518530
;
519531
; RV64-LABEL: insertelt_c6_v8i64_store:
520532
; RV64: # %bb.0:
521-
; RV64-NEXT: andi a1, a1, 7
522-
; RV64-NEXT: slli a1, a1, 3
533+
; RV64-NEXT: slli a1, a1, 32
534+
; RV64-NEXT: srli a1, a1, 29
523535
; RV64-NEXT: add a0, a0, a1
524536
; RV64-NEXT: li a1, 6
525537
; RV64-NEXT: sd a1, 0(a0)

‎llvm/test/CodeGen/X86/pr59980.ll‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@ define void @foo(ptr %0, ptr %1, ptr %2) #0 {
99
; CHECK: ## %bb.0:
1010
; CHECK-NEXT: movl (%rdx), %eax
1111
; CHECK-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0
12-
; CHECK-NEXT: andl $15, %eax
1312
; CHECK-NEXT: vpextrw $0, %xmm0, (%rsi,%rax,2)
1413
; CHECK-NEXT: retq
1514
%4 = bitcast ptr %2 to ptr

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