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[SelectionDAG] Fix off by one error in range check in DAGTypeLegalizer::ExpandShiftByConstant.
The code was considering shifts by an about larger than the number of bits in the original VT to be out of range. Shifts exactly equal to the original bit width are also out of range. I don't know how to test this. DAGCombiner should usually fold this away. I just noticed while looking for something else in this code. The llvm-cov report shows that we don't have coverage for out of range shifts here. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D120170
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llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2468,7 +2468,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
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EVT ShTy = N->getOperand(1).getValueType();
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if (N->getOpcode() == ISD::SHL) {
2471-
if (Amt.ugt(VTBits)) {
2471+
if (Amt.uge(VTBits)) {
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Lo = Hi = DAG.getConstant(0, DL, NVT);
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} else if (Amt.ugt(NVTBits)) {
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Lo = DAG.getConstant(0, DL, NVT);
@@ -2489,7 +2489,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
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}
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if (N->getOpcode() == ISD::SRL) {
2492-
if (Amt.ugt(VTBits)) {
2492+
if (Amt.uge(VTBits)) {
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Lo = Hi = DAG.getConstant(0, DL, NVT);
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} else if (Amt.ugt(NVTBits)) {
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Lo = DAG.getNode(ISD::SRL, DL,
@@ -2510,7 +2510,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt,
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}
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assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
2513-
if (Amt.ugt(VTBits)) {
2513+
if (Amt.uge(VTBits)) {
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Hi = Lo = DAG.getNode(ISD::SRA, DL, NVT, InH,
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DAG.getConstant(NVTBits - 1, DL, ShTy));
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} else if (Amt.ugt(NVTBits)) {

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