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[AArch64][SVE] Implement integer compare intrinsics
Summary: Adds intrinsics for the following: * cmphs, cmphi * cmpge, cmpgt * cmpeq, cmpne * cmplt, cmple * cmplo, cmpls Includes a minor change to `TLI.getMemValueType` that fixes a crash due to the scalable flag being dropped. Reviewers: sdesmalen, efriedma, rengolin, rovka, dancgr, huntergr Reviewed By: efriedma Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70889
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7 files changed

+1792
-35
lines changed

7 files changed

+1792
-35
lines changed

‎llvm/include/llvm/CodeGen/TargetLowering.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1252,7 +1252,7 @@ class TargetLoweringBase {
12521252
Elm = PointerTy.getTypeForEVT(Ty->getContext());
12531253
}
12541254
return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1255-
VTy->getNumElements());
1255+
VTy->getElementCount());
12561256
}
12571257

12581258
return getValueType(DL, Ty, AllowUnknown);

‎llvm/include/llvm/IR/IntrinsicsAArch64.td‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -812,6 +812,13 @@ let TargetPrefix = "aarch64" in { // All intrinsics start with "llvm.aarch64.".
812812
LLVMMatchType<0>],
813813
[IntrNoMem]>;
814814

815+
class AdvSIMD_SVE_CompareWide_Intrinsic
816+
: Intrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
817+
[LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
818+
llvm_anyvector_ty,
819+
llvm_nxv2i64_ty],
820+
[IntrNoMem]>;
821+
815822
class AdvSIMD_SVE_CNT_Intrinsic
816823
: Intrinsic<[LLVMVectorOfBitcastsToInt<0>],
817824
[LLVMVectorOfBitcastsToInt<0>,
@@ -1087,6 +1094,28 @@ def int_aarch64_sve_lsl_wide : AdvSIMD_SVE_ShiftWide_Intrinsic;
10871094
def int_aarch64_sve_lsr : AdvSIMD_Pred2VectorArg_Intrinsic;
10881095
def int_aarch64_sve_lsr_wide : AdvSIMD_SVE_ShiftWide_Intrinsic;
10891096

1097+
//
1098+
// Integer comparisons
1099+
//
1100+
1101+
def int_aarch64_sve_cmpeq : AdvSIMD_SVE_Compare_Intrinsic;
1102+
def int_aarch64_sve_cmpge : AdvSIMD_SVE_Compare_Intrinsic;
1103+
def int_aarch64_sve_cmpgt : AdvSIMD_SVE_Compare_Intrinsic;
1104+
def int_aarch64_sve_cmphi : AdvSIMD_SVE_Compare_Intrinsic;
1105+
def int_aarch64_sve_cmphs : AdvSIMD_SVE_Compare_Intrinsic;
1106+
def int_aarch64_sve_cmpne : AdvSIMD_SVE_Compare_Intrinsic;
1107+
1108+
def int_aarch64_sve_cmpeq_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1109+
def int_aarch64_sve_cmpge_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1110+
def int_aarch64_sve_cmpgt_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1111+
def int_aarch64_sve_cmphi_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1112+
def int_aarch64_sve_cmphs_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1113+
def int_aarch64_sve_cmple_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1114+
def int_aarch64_sve_cmplo_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1115+
def int_aarch64_sve_cmpls_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1116+
def int_aarch64_sve_cmplt_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1117+
def int_aarch64_sve_cmpne_wide : AdvSIMD_SVE_CompareWide_Intrinsic;
1118+
10901119
//
10911120
// Counting bits
10921121
//

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -726,6 +726,13 @@ def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
726726
let PrintMethod = "printImm";
727727
}
728728

729+
def imm0_127_64b : Operand<i64>, ImmLeaf<i64, [{
730+
return ((uint64_t)Imm) < 128;
731+
}]> {
732+
let ParserMatchClass = Imm0_127Operand;
733+
let PrintMethod = "printImm";
734+
}
735+
729736
// NOTE: These imm0_N operands have to be of type i64 because i64 is the size
730737
// for all shift-amounts.
731738

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -735,34 +735,34 @@ let Predicates = [HasSVE] in {
735735
defm TRN1_PPP : sve_int_perm_bin_perm_pp<0b100, "trn1">;
736736
defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2">;
737737

738-
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs">;
739-
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi">;
740-
defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge">;
741-
defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt">;
742-
defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq">;
743-
defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne">;
744-
745-
defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq">;
746-
defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne">;
747-
defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge">;
748-
defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt">;
749-
defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt">;
750-
defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple">;
751-
defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs">;
752-
defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi">;
753-
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo">;
754-
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls">;
755-
756-
defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge">;
757-
defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt">;
758-
defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt">;
759-
defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple">;
760-
defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq">;
761-
defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne">;
762-
defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs">;
763-
defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi">;
764-
defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo">;
765-
defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls">;
738+
defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", int_aarch64_sve_cmphs, SETUGE>;
739+
defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", int_aarch64_sve_cmphi, SETUGT>;
740+
defm CMPGE_PPzZZ : sve_int_cmp_0<0b100, "cmpge", int_aarch64_sve_cmpge, SETGE>;
741+
defm CMPGT_PPzZZ : sve_int_cmp_0<0b101, "cmpgt", int_aarch64_sve_cmpgt, SETGT>;
742+
defm CMPEQ_PPzZZ : sve_int_cmp_0<0b110, "cmpeq", int_aarch64_sve_cmpeq, SETEQ>;
743+
defm CMPNE_PPzZZ : sve_int_cmp_0<0b111, "cmpne", int_aarch64_sve_cmpne, SETNE>;
744+
745+
defm CMPEQ_WIDE_PPzZZ : sve_int_cmp_0_wide<0b010, "cmpeq", int_aarch64_sve_cmpeq_wide>;
746+
defm CMPNE_WIDE_PPzZZ : sve_int_cmp_0_wide<0b011, "cmpne", int_aarch64_sve_cmpne_wide>;
747+
defm CMPGE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b000, "cmpge", int_aarch64_sve_cmpge_wide>;
748+
defm CMPGT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b001, "cmpgt", int_aarch64_sve_cmpgt_wide>;
749+
defm CMPLT_WIDE_PPzZZ : sve_int_cmp_1_wide<0b010, "cmplt", int_aarch64_sve_cmplt_wide>;
750+
defm CMPLE_WIDE_PPzZZ : sve_int_cmp_1_wide<0b011, "cmple", int_aarch64_sve_cmple_wide>;
751+
defm CMPHS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b100, "cmphs", int_aarch64_sve_cmphs_wide>;
752+
defm CMPHI_WIDE_PPzZZ : sve_int_cmp_1_wide<0b101, "cmphi", int_aarch64_sve_cmphi_wide>;
753+
defm CMPLO_WIDE_PPzZZ : sve_int_cmp_1_wide<0b110, "cmplo", int_aarch64_sve_cmplo_wide>;
754+
defm CMPLS_WIDE_PPzZZ : sve_int_cmp_1_wide<0b111, "cmpls", int_aarch64_sve_cmpls_wide>;
755+
756+
defm CMPGE_PPzZI : sve_int_scmp_vi<0b000, "cmpge", SETGE, int_aarch64_sve_cmpge>;
757+
defm CMPGT_PPzZI : sve_int_scmp_vi<0b001, "cmpgt", SETGT, int_aarch64_sve_cmpgt>;
758+
defm CMPLT_PPzZI : sve_int_scmp_vi<0b010, "cmplt", SETLT, null_frag, int_aarch64_sve_cmpgt>;
759+
defm CMPLE_PPzZI : sve_int_scmp_vi<0b011, "cmple", SETLE, null_frag, int_aarch64_sve_cmpge>;
760+
defm CMPEQ_PPzZI : sve_int_scmp_vi<0b100, "cmpeq", SETEQ, int_aarch64_sve_cmpeq>;
761+
defm CMPNE_PPzZI : sve_int_scmp_vi<0b101, "cmpne", SETNE, int_aarch64_sve_cmpne>;
762+
defm CMPHS_PPzZI : sve_int_ucmp_vi<0b00, "cmphs", SETUGE, int_aarch64_sve_cmphs>;
763+
defm CMPHI_PPzZI : sve_int_ucmp_vi<0b01, "cmphi", SETUGT, int_aarch64_sve_cmphi>;
764+
defm CMPLO_PPzZI : sve_int_ucmp_vi<0b10, "cmplo", SETULT, null_frag, int_aarch64_sve_cmphi>;
765+
defm CMPLS_PPzZI : sve_int_ucmp_vi<0b11, "cmpls", SETULE, null_frag, int_aarch64_sve_cmphs>;
766766

767767
defm FCMGE_PPzZZ : sve_fp_3op_p_pd<0b000, "fcmge", int_aarch64_sve_fcmpge>;
768768
defm FCMGT_PPzZZ : sve_fp_3op_p_pd<0b001, "fcmgt", int_aarch64_sve_fcmpgt>;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

Lines changed: 133 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3537,23 +3537,37 @@ class sve_int_cmp<bit cmp_1, bits<2> sz8_64, bits<3> opc, string asm,
35373537
let Defs = [NZCV];
35383538
}
35393539

3540-
multiclass sve_int_cmp_0<bits<3> opc, string asm> {
3540+
multiclass sve_int_cmp_0<bits<3> opc, string asm, SDPatternOperator op,
3541+
CondCode cc> {
35413542
def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR8>;
35423543
def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR16>;
35433544
def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR32>;
35443545
def _D : sve_int_cmp<0b0, 0b11, opc, asm, PPR64, ZPR64, ZPR64>;
3546+
3547+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv16i8, !cast<Instruction>(NAME # _B)>;
3548+
def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv8i16, !cast<Instruction>(NAME # _H)>;
3549+
def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv4i32, !cast<Instruction>(NAME # _S)>;
3550+
def : SVE_3_Op_Pat<nxv2i1, op, nxv2i1, nxv2i64, nxv2i64, !cast<Instruction>(NAME # _D)>;
35453551
}
35463552

3547-
multiclass sve_int_cmp_0_wide<bits<3> opc, string asm> {
3553+
multiclass sve_int_cmp_0_wide<bits<3> opc, string asm, SDPatternOperator op> {
35483554
def _B : sve_int_cmp<0b0, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
35493555
def _H : sve_int_cmp<0b0, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
35503556
def _S : sve_int_cmp<0b0, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3557+
3558+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv2i64, !cast<Instruction>(NAME # _B)>;
3559+
def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv2i64, !cast<Instruction>(NAME # _H)>;
3560+
def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
35513561
}
35523562

3553-
multiclass sve_int_cmp_1_wide<bits<3> opc, string asm> {
3563+
multiclass sve_int_cmp_1_wide<bits<3> opc, string asm, SDPatternOperator op> {
35543564
def _B : sve_int_cmp<0b1, 0b00, opc, asm, PPR8, ZPR8, ZPR64>;
35553565
def _H : sve_int_cmp<0b1, 0b01, opc, asm, PPR16, ZPR16, ZPR64>;
35563566
def _S : sve_int_cmp<0b1, 0b10, opc, asm, PPR32, ZPR32, ZPR64>;
3567+
3568+
def : SVE_3_Op_Pat<nxv16i1, op, nxv16i1, nxv16i8, nxv2i64, !cast<Instruction>(NAME # _B)>;
3569+
def : SVE_3_Op_Pat<nxv8i1, op, nxv8i1, nxv8i16, nxv2i64, !cast<Instruction>(NAME # _H)>;
3570+
def : SVE_3_Op_Pat<nxv4i1, op, nxv4i1, nxv4i32, nxv2i64, !cast<Instruction>(NAME # _S)>;
35573571
}
35583572

35593573

@@ -3585,13 +3599,70 @@ class sve_int_scmp_vi<bits<2> sz8_64, bits<3> opc, string asm, PPRRegOp pprty,
35853599
let Inst{3-0} = Pd;
35863600

35873601
let Defs = [NZCV];
3602+
let ElementSize = pprty.ElementSize;
35883603
}
35893604

3590-
multiclass sve_int_scmp_vi<bits<3> opc, string asm> {
3605+
multiclass sve_int_scmp_vi<bits<3> opc, string asm, CondCode cc,
3606+
SDPatternOperator op = null_frag,
3607+
SDPatternOperator inv_op = null_frag> {
35913608
def _B : sve_int_scmp_vi<0b00, opc, asm, PPR8, ZPR8, simm5_32b>;
35923609
def _H : sve_int_scmp_vi<0b01, opc, asm, PPR16, ZPR16, simm5_32b>;
35933610
def _S : sve_int_scmp_vi<0b10, opc, asm, PPR32, ZPR32, simm5_32b>;
35943611
def _D : sve_int_scmp_vi<0b11, opc, asm, PPR64, ZPR64, simm5_64b>;
3612+
3613+
// IR version
3614+
def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
3615+
(nxv16i8 (AArch64dup (simm5_32b:$imm))),
3616+
cc)),
3617+
(!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, simm5_32b:$imm)>;
3618+
def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
3619+
(nxv8i16 (AArch64dup (simm5_32b:$imm))),
3620+
cc)),
3621+
(!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, simm5_32b:$imm)>;
3622+
def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
3623+
(nxv4i32 (AArch64dup (simm5_32b:$imm))),
3624+
cc)),
3625+
(!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, simm5_32b:$imm)>;
3626+
def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
3627+
(nxv2i64 (AArch64dup (simm5_64b:$imm))),
3628+
cc)),
3629+
(!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, simm5_64b:$imm)>;
3630+
3631+
// Intrinsic version
3632+
def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
3633+
(nxv16i8 ZPR:$Zs1),
3634+
(nxv16i8 (AArch64dup (simm5_32b:$imm))))),
3635+
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3636+
def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
3637+
(nxv8i16 ZPR:$Zs1),
3638+
(nxv8i16 (AArch64dup (simm5_32b:$imm))))),
3639+
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3640+
def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
3641+
(nxv4i32 ZPR:$Zs1),
3642+
(nxv4i32 (AArch64dup (simm5_32b:$imm))))),
3643+
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3644+
def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
3645+
(nxv2i64 ZPR:$Zs1),
3646+
(nxv2i64 (AArch64dup (simm5_64b:$imm))))),
3647+
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
3648+
3649+
// Inverted intrinsic version
3650+
def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
3651+
(nxv16i8 (AArch64dup (simm5_32b:$imm))),
3652+
(nxv16i8 ZPR:$Zs1))),
3653+
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3654+
def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
3655+
(nxv8i16 (AArch64dup (simm5_32b:$imm))),
3656+
(nxv8i16 ZPR:$Zs1))),
3657+
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3658+
def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
3659+
(nxv4i32 (AArch64dup (simm5_32b:$imm))),
3660+
(nxv4i32 ZPR:$Zs1))),
3661+
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, simm5_32b:$imm)>;
3662+
def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
3663+
(nxv2i64 (AArch64dup (simm5_64b:$imm))),
3664+
(nxv2i64 ZPR:$Zs1))),
3665+
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, simm5_64b:$imm)>;
35953666
}
35963667

35973668

@@ -3622,11 +3693,67 @@ class sve_int_ucmp_vi<bits<2> sz8_64, bits<2> opc, string asm, PPRRegOp pprty,
36223693
let Defs = [NZCV];
36233694
}
36243695

3625-
multiclass sve_int_ucmp_vi<bits<2> opc, string asm> {
3696+
multiclass sve_int_ucmp_vi<bits<2> opc, string asm, CondCode cc,
3697+
SDPatternOperator op = null_frag,
3698+
SDPatternOperator inv_op = null_frag> {
36263699
def _B : sve_int_ucmp_vi<0b00, opc, asm, PPR8, ZPR8, imm0_127>;
36273700
def _H : sve_int_ucmp_vi<0b01, opc, asm, PPR16, ZPR16, imm0_127>;
36283701
def _S : sve_int_ucmp_vi<0b10, opc, asm, PPR32, ZPR32, imm0_127>;
3629-
def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127>;
3702+
def _D : sve_int_ucmp_vi<0b11, opc, asm, PPR64, ZPR64, imm0_127_64b>;
3703+
3704+
// IR version
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def : Pat<(nxv16i1 (setcc (nxv16i8 ZPR:$Zs1),
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(nxv16i8 (AArch64dup (imm0_127:$imm))),
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cc)),
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(!cast<Instruction>(NAME # "_B") (PTRUE_B 31), ZPR:$Zs1, imm0_127:$imm)>;
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def : Pat<(nxv8i1 (setcc (nxv8i16 ZPR:$Zs1),
3710+
(nxv8i16 (AArch64dup (imm0_127:$imm))),
3711+
cc)),
3712+
(!cast<Instruction>(NAME # "_H") (PTRUE_H 31), ZPR:$Zs1, imm0_127:$imm)>;
3713+
def : Pat<(nxv4i1 (setcc (nxv4i32 ZPR:$Zs1),
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(nxv4i32 (AArch64dup (imm0_127:$imm))),
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cc)),
3716+
(!cast<Instruction>(NAME # "_S") (PTRUE_S 31), ZPR:$Zs1, imm0_127:$imm)>;
3717+
def : Pat<(nxv2i1 (setcc (nxv2i64 ZPR:$Zs1),
3718+
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
3719+
cc)),
3720+
(!cast<Instruction>(NAME # "_D") (PTRUE_D 31), ZPR:$Zs1, imm0_127_64b:$imm)>;
3721+
3722+
// Intrinsic version
3723+
def : Pat<(nxv16i1 (op (nxv16i1 PPR_3b:$Pg),
3724+
(nxv16i8 ZPR:$Zs1),
3725+
(nxv16i8 (AArch64dup (imm0_127:$imm))))),
3726+
(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3727+
def : Pat<(nxv8i1 (op (nxv8i1 PPR_3b:$Pg),
3728+
(nxv8i16 ZPR:$Zs1),
3729+
(nxv8i16 (AArch64dup (imm0_127:$imm))))),
3730+
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3731+
def : Pat<(nxv4i1 (op (nxv4i1 PPR_3b:$Pg),
3732+
(nxv4i32 ZPR:$Zs1),
3733+
(nxv4i32 (AArch64dup (imm0_127:$imm))))),
3734+
(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3735+
def : Pat<(nxv2i1 (op (nxv2i1 PPR_3b:$Pg),
3736+
(nxv2i64 ZPR:$Zs1),
3737+
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))))),
3738+
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
3739+
3740+
// Inverted intrinsic version
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def : Pat<(nxv16i1 (inv_op (nxv16i1 PPR_3b:$Pg),
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(nxv16i8 (AArch64dup (imm0_127:$imm))),
3743+
(nxv16i8 ZPR:$Zs1))),
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(!cast<Instruction>(NAME # "_B") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3745+
def : Pat<(nxv8i1 (inv_op (nxv8i1 PPR_3b:$Pg),
3746+
(nxv8i16 (AArch64dup (imm0_127:$imm))),
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(nxv8i16 ZPR:$Zs1))),
3748+
(!cast<Instruction>(NAME # "_H") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
3749+
def : Pat<(nxv4i1 (inv_op (nxv4i1 PPR_3b:$Pg),
3750+
(nxv4i32 (AArch64dup (imm0_127:$imm))),
3751+
(nxv4i32 ZPR:$Zs1))),
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(!cast<Instruction>(NAME # "_S") PPR_3b:$Pg, ZPR:$Zs1, imm0_127:$imm)>;
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def : Pat<(nxv2i1 (inv_op (nxv2i1 PPR_3b:$Pg),
3754+
(nxv2i64 (AArch64dup (imm0_127_64b:$imm))),
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(nxv2i64 ZPR:$Zs1))),
3756+
(!cast<Instruction>(NAME # "_D") PPR_3b:$Pg, ZPR:$Zs1, imm0_127_64b:$imm)>;
36303757
}
36313758

36323759

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