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[AMDGPU] Convert some tests to opaque pointers (NFC)
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‎llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll‎

Lines changed: 38 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -13,33 +13,33 @@
1313
; FUNC-LABEL: {{^}}local_address_load:
1414
; SI: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]]
1515
; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
16-
define amdgpu_kernel void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
16+
define amdgpu_kernel void @local_address_load(ptr addrspace(1) %out, ptr addrspace(3) %in) {
1717
entry:
18-
%0 = load i32, i32 addrspace(3)* %in
19-
store i32 %0, i32 addrspace(1)* %out
18+
%0 = load i32, ptr addrspace(3) %in
19+
store i32 %0, ptr addrspace(1) %out
2020
ret void
2121
}
2222

2323
; FUNC-LABEL: {{^}}local_address_gep:
2424
; SI: s_add_i32 [[SPTR:s[0-9]]]
2525
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
2626
; SI: ds_read_b32 [[VPTR]]
27-
define amdgpu_kernel void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
27+
define amdgpu_kernel void @local_address_gep(ptr addrspace(1) %out, ptr addrspace(3) %in, i32 %offset) {
2828
entry:
29-
%0 = getelementptr i32, i32 addrspace(3)* %in, i32 %offset
30-
%1 = load i32, i32 addrspace(3)* %0
31-
store i32 %1, i32 addrspace(1)* %out
29+
%0 = getelementptr i32, ptr addrspace(3) %in, i32 %offset
30+
%1 = load i32, ptr addrspace(3) %0
31+
store i32 %1, ptr addrspace(1) %out
3232
ret void
3333
}
3434

3535
; FUNC-LABEL: {{^}}local_address_gep_const_offset:
3636
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
3737
; SI: ds_read_b32 v{{[0-9]+}}, [[VPTR]] offset:4
38-
define amdgpu_kernel void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
38+
define amdgpu_kernel void @local_address_gep_const_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) {
3939
entry:
40-
%0 = getelementptr i32, i32 addrspace(3)* %in, i32 1
41-
%1 = load i32, i32 addrspace(3)* %0
42-
store i32 %1, i32 addrspace(1)* %out
40+
%0 = getelementptr i32, ptr addrspace(3) %in, i32 1
41+
%1 = load i32, ptr addrspace(3) %0
42+
store i32 %1, ptr addrspace(1) %out
4343
ret void
4444
}
4545

@@ -48,11 +48,11 @@ entry:
4848
; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
4949
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
5050
; SI: ds_read_b32 [[VPTR]]
51-
define amdgpu_kernel void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
51+
define amdgpu_kernel void @local_address_gep_large_const_offset(ptr addrspace(1) %out, ptr addrspace(3) %in) {
5252
entry:
53-
%0 = getelementptr i32, i32 addrspace(3)* %in, i32 16385
54-
%1 = load i32, i32 addrspace(3)* %0
55-
store i32 %1, i32 addrspace(1)* %out
53+
%0 = getelementptr i32, ptr addrspace(3) %in, i32 16385
54+
%1 = load i32, ptr addrspace(3) %0
55+
store i32 %1, ptr addrspace(1) %out
5656
ret void
5757
}
5858

@@ -62,21 +62,21 @@ entry:
6262
; GFX8: s_cmp_lg_u32
6363
; GFX8-NOT: v_cmp_ne_u32
6464
; GFX8: s_cselect_b32
65-
define amdgpu_kernel void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind {
66-
%cmp = icmp ne i32 addrspace(3)* %lds, null
65+
define amdgpu_kernel void @null_32bit_lds_ptr(ptr addrspace(1) %out, ptr addrspace(3) %lds) nounwind {
66+
%cmp = icmp ne ptr addrspace(3) %lds, null
6767
%x = select i1 %cmp, i32 123, i32 456
68-
store i32 %x, i32 addrspace(1)* %out
68+
store i32 %x, ptr addrspace(1) %out
6969
ret void
7070
}
7171

7272
; FUNC-LABEL: {{^}}mul_32bit_ptr:
7373
; SI: s_mul_i32
7474
; SI-NEXT: s_add_i32
7575
; SI: ds_read_b32
76-
define amdgpu_kernel void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
77-
%ptr = getelementptr [3 x float], [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
78-
%val = load float, float addrspace(3)* %ptr
79-
store float %val, float addrspace(1)* %out
76+
define amdgpu_kernel void @mul_32bit_ptr(ptr addrspace(1) %out, ptr addrspace(3) %lds, i32 %tid) {
77+
%ptr = getelementptr [3 x float], ptr addrspace(3) %lds, i32 %tid, i32 0
78+
%val = load float, ptr addrspace(3) %ptr
79+
store float %val, ptr addrspace(1) %out
8080
ret void
8181
}
8282

@@ -85,47 +85,47 @@ define amdgpu_kernel void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] a
8585
; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
8686
; SI: v_mov_b32_e32 [[PTR:v[0-9]+]], 0{{$}}
8787
; SI: ds_read_b32 v{{[0-9]+}}, [[PTR]]
88-
define amdgpu_kernel void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
89-
%val = load float, float addrspace(3)* @g_lds
90-
store float %val, float addrspace(1)* %out
88+
define amdgpu_kernel void @infer_ptr_alignment_global_offset(ptr addrspace(1) %out, i32 %tid) {
89+
%val = load float, ptr addrspace(3) @g_lds
90+
store float %val, ptr addrspace(1) %out
9191
ret void
9292
}
9393

9494

95-
@ptr = addrspace(3) global i32 addrspace(3)* undef
95+
@ptr = addrspace(3) global ptr addrspace(3) undef
9696
@dst = addrspace(3) global [16383 x i32] undef
9797

9898
; FUNC-LABEL: {{^}}global_ptr:
9999
; SI: ds_write_b32
100100
define amdgpu_kernel void @global_ptr() nounwind {
101-
store i32 addrspace(3)* getelementptr ([16383 x i32], [16383 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
101+
store ptr addrspace(3) getelementptr ([16383 x i32], ptr addrspace(3) @dst, i32 0, i32 16), ptr addrspace(3) @ptr
102102
ret void
103103
}
104104

105105
; FUNC-LABEL: {{^}}local_address_store:
106106
; SI: ds_write_b32
107-
define amdgpu_kernel void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
108-
store i32 %val, i32 addrspace(3)* %out
107+
define amdgpu_kernel void @local_address_store(ptr addrspace(3) %out, i32 %val) {
108+
store i32 %val, ptr addrspace(3) %out
109109
ret void
110110
}
111111

112112
; FUNC-LABEL: {{^}}local_address_gep_store:
113113
; SI: s_add_i32 [[SADDR:s[0-9]+]],
114114
; SI: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
115115
; SI: ds_write_b32 [[ADDR]], v{{[0-9]+}}
116-
define amdgpu_kernel void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
117-
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 %offset
118-
store i32 %val, i32 addrspace(3)* %gep, align 4
116+
define amdgpu_kernel void @local_address_gep_store(ptr addrspace(3) %out, i32, i32 %val, i32 %offset) {
117+
%gep = getelementptr i32, ptr addrspace(3) %out, i32 %offset
118+
store i32 %val, ptr addrspace(3) %gep, align 4
119119
ret void
120120
}
121121

122122
; FUNC-LABEL: {{^}}local_address_gep_const_offset_store:
123123
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
124124
; SI: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
125125
; SI: ds_write_b32 [[VPTR]], [[VAL]] offset:4
126-
define amdgpu_kernel void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
127-
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 1
128-
store i32 %val, i32 addrspace(3)* %gep, align 4
126+
define amdgpu_kernel void @local_address_gep_const_offset_store(ptr addrspace(3) %out, i32 %val) {
127+
%gep = getelementptr i32, ptr addrspace(3) %out, i32 1
128+
store i32 %val, ptr addrspace(3) %gep, align 4
129129
ret void
130130
}
131131

@@ -134,8 +134,8 @@ define amdgpu_kernel void @local_address_gep_const_offset_store(i32 addrspace(3)
134134
; SI: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
135135
; SI: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
136136
; SI: ds_write_b32 [[VPTR]], v{{[0-9]+$}}
137-
define amdgpu_kernel void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
138-
%gep = getelementptr i32, i32 addrspace(3)* %out, i32 16385
139-
store i32 %val, i32 addrspace(3)* %gep, align 4
137+
define amdgpu_kernel void @local_address_gep_large_const_offset_store(ptr addrspace(3) %out, i32 %val) {
138+
%gep = getelementptr i32, ptr addrspace(3) %out, i32 16385
139+
store i32 %val, ptr addrspace(3) %gep, align 4
140140
ret void
141141
}

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -109,7 +109,7 @@ define amdgpu_ps { i32, i32 } @sgpr_struct_return_i32_i32(i32 %vgpr0, i32 %vgpr1
109109
ret { i32, i32 } %value
110110
}
111111

112-
define amdgpu_ps i8 addrspace(3)* @sgpr_return_p3i8(i8 addrspace(3)* %vgpr) {
112+
define amdgpu_ps ptr addrspace(3) @sgpr_return_p3i8(ptr addrspace(3) %vgpr) {
113113
; CHECK-LABEL: name: sgpr_return_p3i8
114114
; CHECK: bb.1 (%ir-block.0):
115115
; CHECK-NEXT: liveins: $vgpr0
@@ -119,10 +119,10 @@ define amdgpu_ps i8 addrspace(3)* @sgpr_return_p3i8(i8 addrspace(3)* %vgpr) {
119119
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[PTRTOINT]](s32)
120120
; CHECK-NEXT: $sgpr0 = COPY [[INT]](s32)
121121
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
122-
ret i8 addrspace(3)* %vgpr
122+
ret ptr addrspace(3) %vgpr
123123
}
124124

125-
define amdgpu_ps i8 addrspace(1)* @sgpr_return_p1i8(i8 addrspace(1)* %vgpr) {
125+
define amdgpu_ps ptr addrspace(1) @sgpr_return_p1i8(ptr addrspace(1) %vgpr) {
126126
; CHECK-LABEL: name: sgpr_return_p1i8
127127
; CHECK: bb.1 (%ir-block.0):
128128
; CHECK-NEXT: liveins: $vgpr0, $vgpr1
@@ -136,7 +136,7 @@ define amdgpu_ps i8 addrspace(1)* @sgpr_return_p1i8(i8 addrspace(1)* %vgpr) {
136136
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[UV1]](s32)
137137
; CHECK-NEXT: $sgpr1 = COPY [[INT1]](s32)
138138
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0, implicit $sgpr1
139-
ret i8 addrspace(1)* %vgpr
139+
ret ptr addrspace(1) %vgpr
140140
}
141141

142142
define amdgpu_ps <2 x i16> @sgpr_return_v2i16(<2 x i16> %vgpr) {

‎llvm/test/CodeGen/AMDGPU/InlineAsmCrash.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,10 @@
44
; CHECK-NEXT: s_nop 0
55
; CHECK-NEXT: ;;#ASMEND
66

7-
define void @foo(i32 addrspace(5)* %ptr) #0 {
7+
define void @foo(ptr addrspace(5) %ptr) #0 {
88
%tmp = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "s_nop 0", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65"(i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2)
99
%tmp2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %tmp, 0
10-
store i32 %tmp2, i32 addrspace(5)* %ptr, align 4
10+
store i32 %tmp2, ptr addrspace(5) %ptr, align 4
1111
ret void
1212
}
1313

‎llvm/test/CodeGen/AMDGPU/add-debug.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,13 +3,13 @@
33
; REQUIRES: asserts
44

55
; Check that SelectionDAGDumper does not crash on int_SI_if.
6-
define amdgpu_kernel void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
6+
define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b, i64 %c) {
77
entry:
88
%0 = icmp eq i64 %a, 0
99
br i1 %0, label %if, label %else
1010

1111
if:
12-
%1 = load i64, i64 addrspace(1)* %in
12+
%1 = load i64, ptr addrspace(1) %in
1313
br label %endif
1414

1515
else:
@@ -18,7 +18,7 @@ else:
1818

1919
endif:
2020
%3 = phi i64 [%1, %if], [%2, %else]
21-
store i64 %3, i64 addrspace(1)* %out
21+
store i64 %3, ptr addrspace(1) %out
2222
ret void
2323
}
2424

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