[+] Update AXI inteconnect to support multiple masters to a different slaves at the same time. Implemented like a real interconnect

[!] Slave interface axi_slv treats AXI Light requests as an AXI Full requests, no AW/W accepted at the same time
[*] Default (unmapped) slave device has its slot in config file

Author: sergeykhbr

sv/rtl/internal/ambalib/apb_slv.sv

@@ -17,7 +17,7 @@
 `timescale 1ns/10ps
 
 module apb_slv #(
-    parameter bit async_reset = 1'b0,
+    parameter logic async_reset = 1'b0,
     parameter int unsigned vid = 0,                         // Vendor ID
     parameter int unsigned did = 0                          // Device ID
 )
@@ -41,7 +41,8 @@ import types_amba_pkg::*;
 import types_pnp_pkg::*;
 import apb_slv_pkg::*;
 
-apb_slv_registers r, rin;
+apb_slv_registers r;
+apb_slv_registers rin;
 
 
 always_comb
@@ -51,12 +52,11 @@ begin: comb_proc
     dev_config_type vcfg;
     apb_out_type vapbo;
 
+    v = r;
     vb_rdata = '0;
     vcfg = dev_config_none;
     vapbo = apb_out_none;
 
-    v = r;
-
     vcfg.descrsize = PNP_CFG_DEV_DESCR_BYTES;
     vcfg.descrtype = PNP_CFG_TYPE_SLAVE;
     vcfg.addr_start = i_mapinfo.addr_start;
@@ -100,7 +100,7 @@ begin: comb_proc
     end
     endcase
 
-    if (~async_reset && i_nrst == 1'b0) begin
+    if ((~async_reset) && (i_nrst == 1'b0)) begin
         v = apb_slv_r_reset;
     end
 
@@ -118,26 +118,25 @@ begin: comb_proc
     rin = v;
 end: comb_proc
 
-
 generate
-    if (async_reset) begin: async_rst_gen
+    if (async_reset) begin: async_r_en
 
-        always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
+        always_ff @(posedge i_clk, negedge i_nrst) begin
             if (i_nrst == 1'b0) begin
                 r <= apb_slv_r_reset;
             end else begin
                 r <= rin;
             end
-        end: rg_proc
+        end
 
-    end: async_rst_gen
-    else begin: no_rst_gen
+    end: async_r_en
+    else begin: async_r_dis
 
-        always_ff @(posedge i_clk) begin: rg_proc
+        always_ff @(posedge i_clk) begin
             r <= rin;
-        end: rg_proc
+        end
 
-    end: no_rst_gen
+    end: async_r_dis
 endgenerate
 
 endmodule: apb_slv

sv/rtl/internal/ambalib/apb_slv_pkg.sv

@@ -44,5 +44,4 @@ const apb_slv_registers apb_slv_r_reset = '{
     '0,                                 // resp_rdata
     1'b0                                // resp_err
 };
-
 endpackage: apb_slv_pkg

sv/rtl/internal/ambalib/axi_dma.sv

@@ -19,15 +19,16 @@
 module axi_dma #(
     parameter int abits = 48,                               // adress bits used
     parameter logic async_reset = 1'b0,
-    parameter int userbits = 1
+    parameter int userbits = 1,
+    parameter logic [63:0] base_offset = '0                 // Address offset for all DMA transactions
 )
 (
     input logic i_nrst,                                     // Reset: active LOW
     input logic i_clk,                                      // CPU clock
     output logic o_req_mem_ready,                           // Ready to accept next data
     input logic i_req_mem_valid,                            // Request data is ready to accept
     input logic i_req_mem_write,                            // 0=read; 1=write operation
-    input logic [9:0] i_req_mem_bytes,                      // 0=1024 B; 4=DWORD; 8=QWORD; ...
+    input logic [11:0] i_req_mem_bytes,                     // 0=4096 B; 4=DWORD; 8=QWORD; ...
     input logic [abits-1:0] i_req_mem_addr,                 // Address to read/write
     input logic [7:0] i_req_mem_strob,                      // Byte enabling write strob
     input logic [63:0] i_req_mem_data,                      // Data to write
@@ -108,7 +109,7 @@ axi_dma_registers rin;
 always_comb
 begin: comb_proc
     axi_dma_registers v;
-    logic [9:0] vb_req_mem_bytes_m1;
+    logic [11:0] vb_req_mem_bytes_m1;
     logic [CFG_SYSBUS_ADDR_BITS-1:0] vb_req_addr_inc;
     logic [CFG_SYSBUS_DATA_BITS-1:0] vb_r_data_swap;
     axi4_master_out_type vmsto;
@@ -124,7 +125,7 @@ begin: comb_proc
 
     // Byte swapping:
     if (r.req_size == 3'd0) begin
-        vb_req_addr_inc[9: 0] = (r.req_addr[9: 0] + 10'h001);
+        vb_req_addr_inc[11: 0] = (r.req_addr[11: 0] + 12'h001);
         if (r.req_addr[2: 0] == 3'd0) begin
             vb_r_data_swap[31: 0] = {i_msti.r_data[7: 0], i_msti.r_data[7: 0], i_msti.r_data[7: 0], i_msti.r_data[7: 0]};
         end else if (r.req_addr[2: 0] == 3'd1) begin
@@ -144,7 +145,7 @@ begin: comb_proc
         end
         vb_r_data_swap[63: 32] = vb_r_data_swap[31: 0];
     end else if (r.req_size == 3'd1) begin
-        vb_req_addr_inc[9: 0] = (r.req_addr[9: 0] + 10'h002);
+        vb_req_addr_inc[11: 0] = (r.req_addr[11: 0] + 12'h002);
         if (r.req_addr[2: 1] == 2'd0) begin
             vb_r_data_swap = {i_msti.r_data[15: 0], i_msti.r_data[15: 0], i_msti.r_data[15: 0], i_msti.r_data[15: 0]};
         end else if (r.req_addr[2: 1] == 2'd1) begin
@@ -155,14 +156,14 @@ begin: comb_proc
             vb_r_data_swap = {i_msti.r_data[63: 48], i_msti.r_data[63: 48], i_msti.r_data[63: 48], i_msti.r_data[63: 48]};
         end
     end else if (r.req_size == 3'd2) begin
-        vb_req_addr_inc[9: 0] = (r.req_addr[9: 0] + 10'h004);
+        vb_req_addr_inc[11: 0] = (r.req_addr[11: 0] + 12'h004);
         if (r.req_addr[2] == 1'b0) begin
             vb_r_data_swap = {i_msti.r_data[31: 0], i_msti.r_data[31: 0]};
         end else begin
             vb_r_data_swap = {i_msti.r_data[63: 32], i_msti.r_data[63: 32]};
         end
     end else begin
-        vb_req_addr_inc[9: 0] = (r.req_addr[9: 0] + 10'h008);
+        vb_req_addr_inc[11: 0] = (r.req_addr[11: 0] + 12'h008);
         vb_r_data_swap = i_msti.r_data;
     end
 
@@ -174,19 +175,19 @@ begin: comb_proc
         v.resp_last = 1'b0;
         if (i_req_mem_valid == 1'b1) begin
             v.req_ready = 1'b0;
-            v.req_addr = {'0, i_req_mem_addr};
-            if (i_req_mem_bytes == 10'd1) begin
+            v.req_addr = {base_offset[(CFG_SYSBUS_ADDR_BITS - 1): abits], i_req_mem_addr};
+            if (i_req_mem_bytes == 12'd1) begin
                 v.req_size = 3'd0;
                 v.req_len = 8'd0;
-            end else if (i_req_mem_bytes == 10'd2) begin
+            end else if (i_req_mem_bytes == 12'd2) begin
                 v.req_size = 3'd1;
                 v.req_len = 8'd0;
-            end else if (i_req_mem_bytes == 10'd4) begin
+            end else if (i_req_mem_bytes == 12'd4) begin
                 v.req_size = 3'd2;
                 v.req_len = 8'd0;
             end else begin
                 v.req_size = 3'd3;
-                v.req_len = {1'b0, vb_req_mem_bytes_m1[9: 3]};
+                v.req_len = vb_req_mem_bytes_m1[10: 3];
             end
             if (i_req_mem_write == 1'b0) begin
                 v.ar_valid = 1'b1;
@@ -206,7 +207,6 @@ begin: comb_proc
             // debug interface:
             v.dbg_payload = {1'b1,
                     i_req_mem_addr[10: 0],
-                    2'h0,
                     i_req_mem_bytes,
                     i_req_mem_strob,
                     i_req_mem_data[31: 0]};