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sergeykhbrsergeykhbr
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[+] Update folder structure to support different target:
- riscv_soc renamed to gencpu64. Gpu3d and minimal32 will be added later. - split RTL folder on internal and techmap (external IP). External will be re-organized with next commits
1 parent 6bdfd61 commit 8f9e4ec

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169 files changed

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lines changed

‎sv/prj/common/lists/ambalib.f‎

Lines changed: 6 additions & 12 deletions
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@@ -1,12 +1,6 @@
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${RTL_HOME}/ambalib/types_amba_pkg.sv
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${RTL_HOME}/ambalib/types_bus0_pkg.sv
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${RTL_HOME}/ambalib/types_bus1_pkg.sv
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${RTL_HOME}/ambalib/types_pnp_pkg.sv
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${RTL_HOME}/ambalib/axictrl_bus0_pkg.sv
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${RTL_HOME}/ambalib/axi2apb_bus1_pkg.sv
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${RTL_HOME}/ambalib/apb_slv_pkg.sv
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${RTL_HOME}/ambalib/apb_slv.sv
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${RTL_HOME}/ambalib/axi_slv_pkg.sv
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${RTL_HOME}/ambalib/axi_slv.sv
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${RTL_HOME}/ambalib/axictrl_bus0.sv
12-
${RTL_HOME}/ambalib/axi2apb_bus1.sv
1+
${RTL_HOME}/internal/ambalib/types_amba_pkg.sv
2+
${RTL_HOME}/internal/ambalib/types_pnp_pkg.sv
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${RTL_HOME}/internal/ambalib/apb_slv_pkg.sv
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${RTL_HOME}/internal/ambalib/apb_slv.sv
5+
${RTL_HOME}/internal/ambalib/axi_slv_pkg.sv
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${RTL_HOME}/internal/ambalib/axi_slv.sv

‎sv/prj/common/lists/gencpu64_soc.f‎

Lines changed: 8 additions & 0 deletions
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${RTL_HOME}/internal/gencpu64/types_gencpu64_bus0_pkg.sv
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${RTL_HOME}/internal/gencpu64/gencpu64_axictrl_bus0_pkg.sv
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${RTL_HOME}/internal/gencpu64/gencpu64_axictrl_bus0.sv
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${RTL_HOME}/internal/gencpu64/types_gencpu64_bus1_pkg.sv
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${RTL_HOME}/internal/gencpu64/gencpu64_axi2apb_bus1_pkg.sv
6+
${RTL_HOME}/internal/gencpu64/gencpu64_axi2apb_bus1.sv
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${RTL_HOME}/internal/gencpu64/gencpu64_soc_pkg.sv
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${RTL_HOME}/internal/gencpu64/gencpu64_soc.sv

‎sv/prj/common/lists/misclib.f‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
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${RTL_HOME}/misclib/sfifo.sv
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${RTL_HOME}/misclib/apb_prci_pkg.sv
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${RTL_HOME}/misclib/apb_prci.sv
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${RTL_HOME}/misclib/apb_ddr_pkg.sv
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${RTL_HOME}/misclib/apb_ddr.sv
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${RTL_HOME}/misclib/apb_uart.sv
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${RTL_HOME}/misclib/apb_gpio.sv
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${RTL_HOME}/misclib/apb_spi.sv
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${RTL_HOME}/misclib/apb_pnp.sv
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${RTL_HOME}/misclib/axi_rom.sv
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${RTL_HOME}/misclib/axi_sram.sv
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${RTL_HOME}/misclib/clint.sv
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${RTL_HOME}/misclib/plic.sv
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${RTL_HOME}/internal/misclib/sfifo.sv
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${RTL_HOME}/internal/misclib/apb_prci_pkg.sv
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${RTL_HOME}/internal/misclib/apb_prci.sv
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${RTL_HOME}/internal/misclib/apb_ddr_pkg.sv
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${RTL_HOME}/internal/misclib/apb_ddr.sv
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${RTL_HOME}/internal/misclib/apb_uart.sv
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${RTL_HOME}/internal/misclib/apb_gpio.sv
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${RTL_HOME}/internal/misclib/apb_spi.sv
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${RTL_HOME}/internal/misclib/apb_pnp.sv
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${RTL_HOME}/internal/misclib/axi_rom.sv
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${RTL_HOME}/internal/misclib/axi_sram.sv
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${RTL_HOME}/internal/misclib/clint.sv
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${RTL_HOME}/internal/misclib/plic.sv

‎sv/prj/common/lists/riscv_soc.f‎

Lines changed: 0 additions & 2 deletions
This file was deleted.

‎sv/prj/common/lists/riverlib.f‎

Lines changed: 111 additions & 111 deletions
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1-
${RTL_HOME}/riverlib/river_cfg_pkg.sv
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${RTL_HOME}/riverlib/types_river_pkg.sv
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${RTL_HOME}/riverlib/river_top_pkg.sv
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${RTL_HOME}/riverlib/river_amba_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2dummy_pkg.sv
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${RTL_HOME}/riverlib/dummycpu_pkg.sv
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${RTL_HOME}/riverlib/workgroup_pkg.sv
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${RTL_HOME}/riverlib/core/regibank_pkg.sv
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${RTL_HOME}/riverlib/core/proc_pkg.sv
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${RTL_HOME}/riverlib/core/mmu_pkg.sv
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${RTL_HOME}/riverlib/core/csr_pkg.sv
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${RTL_HOME}/riverlib/core/arith/alu_logic_pkg.sv
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${RTL_HOME}/riverlib/core/arith/int_mul_pkg.sv
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${RTL_HOME}/riverlib/core/arith/divstage64_pkg.sv
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${RTL_HOME}/riverlib/core/arith/int_div_pkg.sv
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${RTL_HOME}/riverlib/core/arith/int_addsub_pkg.sv
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${RTL_HOME}/riverlib/core/arith/shift_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/fdiv_d_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/divstage53_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/fmul_d_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/d2l_d_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/idiv53_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/l2d_d_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/imul53_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/fadd_d_pkg.sv
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${RTL_HOME}/riverlib/core/fpu_d/fpu_top_pkg.sv
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${RTL_HOME}/riverlib/core/ic_csr_m2_s1_pkg.sv
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${RTL_HOME}/riverlib/ic_axi4_to_l1_pkg.sv
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${RTL_HOME}/riverlib/core/dbg_port_pkg.sv
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${RTL_HOME}/riverlib/core/fetch_pkg.sv
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${RTL_HOME}/riverlib/core/bp_pkg.sv
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${RTL_HOME}/riverlib/core/bp_predec_pkg.sv
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${RTL_HOME}/riverlib/core/bp_btb_pkg.sv
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${RTL_HOME}/riverlib/core/dec_rv_pkg.sv
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${RTL_HOME}/riverlib/core/dec_rvc_pkg.sv
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${RTL_HOME}/riverlib/core/decoder_pkg.sv
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${RTL_HOME}/riverlib/core/execute_pkg.sv
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${RTL_HOME}/riverlib/core/memaccess_pkg.sv
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${RTL_HOME}/riverlib/core/stacktrbuf_pkg.sv
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${RTL_HOME}/riverlib/core/tracer_pkg.sv
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${RTL_HOME}/riverlib/core/arith/divstage64.sv
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${RTL_HOME}/riverlib/core/arith/int_mul.sv
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${RTL_HOME}/riverlib/core/arith/int_div.sv
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${RTL_HOME}/riverlib/core/arith/shift.sv
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${RTL_HOME}/riverlib/core/arith/alu_logic.sv
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${RTL_HOME}/riverlib/core/arith/int_addsub.sv
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${RTL_HOME}/riverlib/core/fpu_d/divstage53.sv
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${RTL_HOME}/riverlib/core/fpu_d/zeroenc.sv
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${RTL_HOME}/riverlib/core/fpu_d/imul53.sv
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${RTL_HOME}/riverlib/core/fpu_d/fmul_d.sv
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${RTL_HOME}/riverlib/core/fpu_d/d2l_d.sv
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${RTL_HOME}/riverlib/core/fpu_d/idiv53.sv
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${RTL_HOME}/riverlib/core/fpu_d/fdiv_d.sv
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${RTL_HOME}/riverlib/core/fpu_d/l2d_d.sv
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${RTL_HOME}/riverlib/core/fpu_d/fadd_d.sv
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${RTL_HOME}/riverlib/core/fpu_d/fpu_top.sv
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${RTL_HOME}/riverlib/core/queue.sv
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${RTL_HOME}/riverlib/core/mmu.sv
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${RTL_HOME}/riverlib/core/proc.sv
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${RTL_HOME}/riverlib/core/memaccess.sv
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${RTL_HOME}/riverlib/core/execute.sv
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${RTL_HOME}/riverlib/core/ic_csr_m2_s1.sv
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${RTL_HOME}/riverlib/core/csr.sv
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${RTL_HOME}/riverlib/core/stacktrbuf.sv
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${RTL_HOME}/riverlib/core/dec_rv.sv
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${RTL_HOME}/riverlib/core/dec_rvc.sv
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${RTL_HOME}/riverlib/core/decoder.sv
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${RTL_HOME}/riverlib/core/regibank.sv
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${RTL_HOME}/riverlib/core/fetch.sv
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${RTL_HOME}/riverlib/core/bp.sv
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${RTL_HOME}/riverlib/core/bp_predec.sv
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${RTL_HOME}/riverlib/core/bp_btb.sv
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${RTL_HOME}/riverlib/core/dbg_port.sv
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${RTL_HOME}/riverlib/core/tracer.sv
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${RTL_HOME}/riverlib/cache/icache_lru_pkg.sv
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${RTL_HOME}/riverlib/cache/dcache_lru_pkg.sv
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${RTL_HOME}/riverlib/cache/pma_pkg.sv
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${RTL_HOME}/riverlib/cache/pmp_pkg.sv
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${RTL_HOME}/riverlib/cache/cache_top_pkg.sv
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${RTL_HOME}/riverlib/cache/tagmem.sv
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${RTL_HOME}/riverlib/cache/lrunway.sv
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${RTL_HOME}/riverlib/cache/tagmemcoupled.sv
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${RTL_HOME}/riverlib/cache/tagmemnway.sv
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${RTL_HOME}/riverlib/cache/dcache_lru.sv
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${RTL_HOME}/riverlib/cache/icache_lru.sv
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${RTL_HOME}/riverlib/river_top.sv
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${RTL_HOME}/riverlib/river_amba.sv
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${RTL_HOME}/riverlib/ic_axi4_to_l1.sv
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${RTL_HOME}/riverlib/dmi/dmidebug_pkg.sv
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${RTL_HOME}/riverlib/dmi/ic_dport_pkg.sv
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${RTL_HOME}/riverlib/dmi/jtagcdc_pkg.sv
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${RTL_HOME}/riverlib/dmi/jtagtap.sv
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${RTL_HOME}/riverlib/dmi/jtagcdc.sv
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${RTL_HOME}/riverlib/dmi/dmidebug.sv
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${RTL_HOME}/riverlib/dmi/ic_dport.sv
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${RTL_HOME}/riverlib/l2cache/l2cache_lru_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2serdes_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2_amba_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2_dst_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2_top_pkg.sv
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${RTL_HOME}/riverlib/l2cache/l2cache_lru.sv
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${RTL_HOME}/riverlib/l2cache/l2serdes.sv
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${RTL_HOME}/riverlib/l2cache/l2_amba.sv
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${RTL_HOME}/riverlib/l2cache/l2_top.sv
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${RTL_HOME}/riverlib/l2cache/l2dummy.sv
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${RTL_HOME}/riverlib/dummycpu.sv
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${RTL_HOME}/riverlib/workgroup.sv
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${RTL_HOME}/internal/riverlib/river_cfg_pkg.sv
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${RTL_HOME}/internal/riverlib/types_river_pkg.sv
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${RTL_HOME}/internal/riverlib/river_top_pkg.sv
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${RTL_HOME}/internal/riverlib/river_amba_pkg.sv
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${RTL_HOME}/internal/riverlib/l2cache/l2dummy_pkg.sv
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${RTL_HOME}/internal/riverlib/dummycpu_pkg.sv
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${RTL_HOME}/internal/riverlib/workgroup_pkg.sv
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${RTL_HOME}/internal/riverlib/core/regibank_pkg.sv
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${RTL_HOME}/internal/riverlib/core/proc_pkg.sv
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${RTL_HOME}/internal/riverlib/core/mmu_pkg.sv
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${RTL_HOME}/internal/riverlib/core/csr_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/alu_logic_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_mul_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/divstage64_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_div_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_addsub_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/shift_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fdiv_d_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/divstage53_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fmul_d_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/d2l_d_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/idiv53_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/l2d_d_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/imul53_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fadd_d_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fpu_top_pkg.sv
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${RTL_HOME}/internal/riverlib/core/ic_csr_m2_s1_pkg.sv
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${RTL_HOME}/internal/riverlib/ic_axi4_to_l1_pkg.sv
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${RTL_HOME}/internal/riverlib/core/dbg_port_pkg.sv
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${RTL_HOME}/internal/riverlib/core/fetch_pkg.sv
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${RTL_HOME}/internal/riverlib/core/bp_pkg.sv
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${RTL_HOME}/internal/riverlib/core/bp_predec_pkg.sv
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${RTL_HOME}/internal/riverlib/core/bp_btb_pkg.sv
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${RTL_HOME}/internal/riverlib/core/dec_rv_pkg.sv
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${RTL_HOME}/internal/riverlib/core/dec_rvc_pkg.sv
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${RTL_HOME}/internal/riverlib/core/decoder_pkg.sv
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${RTL_HOME}/internal/riverlib/core/execute_pkg.sv
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${RTL_HOME}/internal/riverlib/core/memaccess_pkg.sv
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${RTL_HOME}/internal/riverlib/core/stacktrbuf_pkg.sv
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${RTL_HOME}/internal/riverlib/core/tracer_pkg.sv
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${RTL_HOME}/internal/riverlib/core/arith/divstage64.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_mul.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_div.sv
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${RTL_HOME}/internal/riverlib/core/arith/shift.sv
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${RTL_HOME}/internal/riverlib/core/arith/alu_logic.sv
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${RTL_HOME}/internal/riverlib/core/arith/int_addsub.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/divstage53.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/zeroenc.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/idiv53.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fdiv_d.sv
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${RTL_HOME}/internal/riverlib/core/fpu_d/fadd_d.sv
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${RTL_HOME}/internal/riverlib/core/mmu.sv
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${RTL_HOME}/internal/riverlib/core/proc.sv
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${RTL_HOME}/internal/riverlib/core/fetch.sv
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${RTL_HOME}/internal/riverlib/workgroup.sv

‎sv/prj/common/lists/sdctrl.f‎

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${RTL_HOME}/sdctrl/sdctrl_cfg_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_regs_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_regs.sv
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${RTL_HOME}/sdctrl/sdctrl_crc7_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_crc7.sv
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${RTL_HOME}/sdctrl/sdctrl_crc16_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_crc16.sv
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${RTL_HOME}/sdctrl/sdctrl_err_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_err.sv
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${RTL_HOME}/sdctrl/sdctrl_wdog_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_wdog.sv
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${RTL_HOME}/sdctrl/sdctrl_spimode_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_spimode.sv
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${RTL_HOME}/sdctrl/sdctrl_sdmode_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_sdmode.sv
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${RTL_HOME}/sdctrl/sdctrl_cmd_transmitter_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_cmd_transmitter.sv
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${RTL_HOME}/sdctrl/sdctrl_cache_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl_cache.sv
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${RTL_HOME}/sdctrl/sdctrl_pkg.sv
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${RTL_HOME}/sdctrl/sdctrl.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_cfg_pkg.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_regs_pkg.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_regs.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_crc7_pkg.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_crc7.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_crc16_pkg.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_crc16.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_err_pkg.sv
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${RTL_HOME}/internal/sdctrl/sdctrl_err.sv
10+
${RTL_HOME}/internal/sdctrl/sdctrl_wdog_pkg.sv
11+
${RTL_HOME}/internal/sdctrl/sdctrl_wdog.sv
12+
${RTL_HOME}/internal/sdctrl/sdctrl_spimode_pkg.sv
13+
${RTL_HOME}/internal/sdctrl/sdctrl_spimode.sv
14+
${RTL_HOME}/internal/sdctrl/sdctrl_sdmode_pkg.sv
15+
${RTL_HOME}/internal/sdctrl/sdctrl_sdmode.sv
16+
${RTL_HOME}/internal/sdctrl/sdctrl_cmd_transmitter_pkg.sv
17+
${RTL_HOME}/internal/sdctrl/sdctrl_cmd_transmitter.sv
18+
${RTL_HOME}/internal/sdctrl/sdctrl_cache_pkg.sv
19+
${RTL_HOME}/internal/sdctrl/sdctrl_cache.sv
20+
${RTL_HOME}/internal/sdctrl/sdctrl_pkg.sv
21+
${RTL_HOME}/internal/sdctrl/sdctrl.sv

‎sv/prj/impl/asic/asic_top.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -211,7 +211,7 @@ iobuf_tech iosddat3 (
211211
.o_apbo(prci_apbo)
212212
);
213213

214-
riscv_soc #(
214+
gencpu64_soc #(
215215
.async_reset(async_reset),
216216
.sim_uart_speedup_rate(sim_uart_speedup_rate)
217217
) soc0 (

‎sv/prj/impl/asic_sim/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ comp: prep clr_logs
5151
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/techmap.f
5252
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/misclib.f
5353
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/sdctrl.f
54-
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/riscv_soc.f
54+
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/gencpu64_soc.f
5555
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ../asic/asic_top.f
5656
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f asic_top_sim.f
5757

@@ -81,7 +81,7 @@ mce_flow: prep clr_logs
8181
-f ${LISTS_HOME}/techmap.f \
8282
-f ${LISTS_HOME}/misclib.f \
8383
-f ${LISTS_HOME}/sdctrl.f \
84-
-f ${LISTS_HOME}/riscv_soc.f \
84+
-f ${LISTS_HOME}/gencpu64_soc.f \
8585
-f ../asic/asic_top.f \
8686
-f asic_top_sim.f \
8787
-top asic_top_tb \

‎sv/prj/impl/kc705/kc705_top.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,7 @@ iobuf_tech iosddat3 (
233233
);
234234

235235

236-
riscv_soc #(
236+
gencpu64_soc #(
237237
.async_reset(async_reset),
238238
.sim_uart_speedup_rate(sim_uart_speedup_rate)
239239
) soc0 (

‎sv/prj/impl/kc705_sim/Makefile‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ comp: prep clr_logs
5353
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/techmap_ddr_kc705.f
5454
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/misclib.f
5555
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/sdctrl.f
56-
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/riscv_soc.f
56+
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ${LISTS_HOME}/gencpu64_soc.f
5757
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f ../kc705/kc705_top.f
5858
${SRUN} xmvlog ${VLOG_PARAMS_TB} ${INC} ${GLOBAL_DEFINE} -f kc705_top_sim.f
5959

@@ -84,7 +84,7 @@ mce_flow: prep clr_logs
8484
-f ${LISTS_HOME}/techmap_ddr_kc705.f \
8585
-f ${LISTS_HOME}/misclib.f \
8686
-f ${LISTS_HOME}/sdctrl.f \
87-
-f ${LISTS_HOME}/riscv_soc.f \
87+
-f ${LISTS_HOME}/gencpu64_soc.f \
8888
-f ../kc705/kc705_top.f \
8989
-f kc705_top_sim.f \
9090
-top kc705_top_tb \

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