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sergeykhbrsergeykhbr
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[*] Regenerate sdctrl folder. Merging with the latest rtlgen output
1 parent ec0eeb4 commit a8eb2fb

21 files changed

+134
-148
lines changed

‎sv/prj/common/lists/misclib.f‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,8 @@
66
${RTL_HOME}/internal/misclib/apb_uart.sv
77
${RTL_HOME}/internal/misclib/apb_gpio.sv
88
${RTL_HOME}/internal/misclib/apb_spi.sv
9+
${RTL_HOME}/internal/misclib/apb_i2c_pkg.sv
10+
${RTL_HOME}/internal/misclib/apb_i2c.sv
911
${RTL_HOME}/internal/misclib/apb_pnp.sv
1012
${RTL_HOME}/internal/misclib/axi_rom.sv
1113
${RTL_HOME}/internal/misclib/axi_sram.sv

‎sv/rtl/internal/sdctrl/sdctrl.sv‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
`timescale 1ns/10ps
1818

1919
module sdctrl #(
20-
parameter bit async_reset = 1'b0
20+
parameter logic async_reset = 1'b0
2121
)
2222
(
2323
input logic i_clk, // CPU clock
@@ -165,7 +165,8 @@ logic [2:0] wb_sdtype;
165165
logic w_wdog_ena;
166166
logic w_crc16_clear;
167167
logic w_crc16_next;
168-
sdctrl_registers r, rin;
168+
sdctrl_registers r;
169+
sdctrl_registers rin;
169170

170171
axi_slv #(
171172
.async_reset(async_reset),
@@ -480,6 +481,7 @@ begin: comb_proc
480481
logic v_crc16_clear;
481482
logic v_crc16_next;
482483

484+
v = r;
483485
v_cmd_dir = DIR_OUTPUT;
484486
v_cmd_in = 1'b0;
485487
v_cmd_out = 1'b1;
@@ -507,8 +509,6 @@ begin: comb_proc
507509
v_crc16_clear = 1'b0;
508510
v_crc16_next = 1'b0;
509511

510-
v = r;
511-
512512

513513
if (r.mode == MODE_PRE_INIT) begin
514514
// Page 222, Fig.4-96 State Diagram (Pre-Init mode)
@@ -591,7 +591,7 @@ begin: comb_proc
591591
v_crc16_next = w_sd_crc16_next;
592592
end
593593

594-
if (~async_reset && i_nrst == 1'b0) begin
594+
if ((~async_reset) && (i_nrst == 1'b0)) begin
595595
v = sdctrl_r_reset;
596596
end
597597

@@ -627,26 +627,25 @@ begin: comb_proc
627627
rin = v;
628628
end: comb_proc
629629

630-
631630
generate
632-
if (async_reset) begin: async_rst_gen
631+
if (async_reset) begin: async_r_en
633632

634-
always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
633+
always_ff @(posedge i_clk, negedge i_nrst) begin
635634
if (i_nrst == 1'b0) begin
636635
r <= sdctrl_r_reset;
637636
end else begin
638637
r <= rin;
639638
end
640-
end: rg_proc
639+
end
641640

642-
end: async_rst_gen
643-
else begin: no_rst_gen
641+
end: async_r_en
642+
else begin: async_r_dis
644643

645-
always_ff @(posedge i_clk) begin: rg_proc
644+
always_ff @(posedge i_clk) begin
646645
r <= rin;
647-
end: rg_proc
646+
end
648647

649-
end: no_rst_gen
648+
end: async_r_dis
650649
endgenerate
651650

652651
endmodule: sdctrl

‎sv/rtl/internal/sdctrl/sdctrl_cache.sv‎

Lines changed: 15 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
`timescale 1ns/10ps
1818

1919
module sdctrl_cache #(
20-
parameter bit async_reset = 1'b0
20+
parameter logic async_reset = 1'b0
2121
)
2222
(
2323
input logic i_clk, // CPU clock
@@ -60,15 +60,16 @@ logic line_hit_o;
6060
// Snoop signals:
6161
logic [CFG_SDCACHE_ADDR_BITS-1:0] line_snoop_addr_i;
6262
logic [SDCACHE_FL_TOTAL-1:0] line_snoop_flags_o;
63-
sdctrl_cache_registers r, rin;
63+
sdctrl_cache_registers r;
64+
sdctrl_cache_registers rin;
6465

6566
TagMem #(
66-
.async_reset(async_reset),
6767
.abus(abus),
6868
.ibits(ibits),
6969
.lnbits(lnbits),
7070
.flbits(flbits),
71-
.snoop(0)
71+
.snoop(0),
72+
.async_reset(async_reset)
7273
) mem0 (
7374
.i_clk(i_clk),
7475
.i_nrst(i_nrst),
@@ -106,6 +107,7 @@ begin: comb_proc
106107
logic v_mem_addr_last;
107108
logic [CFG_SDCACHE_ADDR_BITS-1:0] vb_addr_direct_next;
108109

110+
v = r;
109111
vb_cache_line_i_modified = '0;
110112
vb_line_rdata_o_modified = '0;
111113
vb_line_rdata_o_wstrb = '0;
@@ -125,8 +127,6 @@ begin: comb_proc
125127
v_mem_addr_last = 1'b0;
126128
vb_addr_direct_next = '0;
127129

128-
v = r;
129-
130130
ridx = r.req_addr[(CFG_LOG2_SDCACHE_BYTES_PER_LINE - 1): 3];
131131
v_mem_addr_last = (&r.mem_addr[9: CFG_LOG2_SDCACHE_BYTES_PER_LINE]);
132132

@@ -347,7 +347,7 @@ begin: comb_proc
347347
end
348348
endcase
349349

350-
if (~async_reset && i_nrst == 1'b0) begin
350+
if ((~async_reset) && (i_nrst == 1'b0)) begin
351351
v = sdctrl_cache_r_reset;
352352
end
353353

@@ -371,26 +371,25 @@ begin: comb_proc
371371
rin = v;
372372
end: comb_proc
373373

374-
375374
generate
376-
if (async_reset) begin: async_rst_gen
375+
if (async_reset) begin: async_r_en
377376

378-
always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
377+
always_ff @(posedge i_clk, negedge i_nrst) begin
379378
if (i_nrst == 1'b0) begin
380379
r <= sdctrl_cache_r_reset;
381380
end else begin
382381
r <= rin;
383382
end
384-
end: rg_proc
383+
end
385384

386-
end: async_rst_gen
387-
else begin: no_rst_gen
385+
end: async_r_en
386+
else begin: async_r_dis
388387

389-
always_ff @(posedge i_clk) begin: rg_proc
388+
always_ff @(posedge i_clk) begin
390389
r <= rin;
391-
end: rg_proc
390+
end
392391

393-
end: no_rst_gen
392+
end: async_r_dis
394393
endgenerate
395394

396395
endmodule: sdctrl_cache

‎sv/rtl/internal/sdctrl/sdctrl_cache_pkg.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -76,5 +76,4 @@ const sdctrl_cache_registers sdctrl_cache_r_reset = '{
7676
'0, // cache_line_i
7777
'0 // cache_line_o
7878
};
79-
8079
endpackage: sdctrl_cache_pkg

‎sv/rtl/internal/sdctrl/sdctrl_cmd_transmitter.sv‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
`timescale 1ns/10ps
1818

1919
module sdctrl_cmd_transmitter #(
20-
parameter bit async_reset = 1'b0
20+
parameter logic async_reset = 1'b0
2121
)
2222
(
2323
input logic i_clk, // CPU clock
@@ -55,7 +55,8 @@ import sdctrl_cmd_transmitter_pkg::*;
5555
logic [6:0] wb_crc7;
5656
logic w_crc7_next;
5757
logic w_crc7_dat;
58-
sdctrl_cmd_transmitter_registers r, rin;
58+
sdctrl_cmd_transmitter_registers r;
59+
sdctrl_cmd_transmitter_registers rin;
5960

6061
sdctrl_crc7 #(
6162
.async_reset(async_reset)
@@ -77,14 +78,13 @@ begin: comb_proc
7778
logic v_crc7_dat;
7879
logic v_crc7_next;
7980

81+
v = r;
8082
v_req_ready = 1'b0;
8183
vb_cmdshift = '0;
8284
vb_resp_spistatus = '0;
8385
v_crc7_dat = 1'b0;
8486
v_crc7_next = 1'b0;
8587

86-
v = r;
87-
8888
vb_cmdshift = r.cmdshift;
8989
vb_resp_spistatus = r.resp_spistatus;
9090
v.err_valid = 1'b0;
@@ -290,7 +290,7 @@ begin: comb_proc
290290
v_crc7_dat = i_cmd;
291291
end
292292

293-
if (~async_reset && i_nrst == 1'b0) begin
293+
if ((~async_reset) && (i_nrst == 1'b0)) begin
294294
v = sdctrl_cmd_transmitter_r_reset;
295295
end
296296

@@ -313,26 +313,25 @@ begin: comb_proc
313313
rin = v;
314314
end: comb_proc
315315

316-
317316
generate
318-
if (async_reset) begin: async_rst_gen
317+
if (async_reset) begin: async_r_en
319318

320-
always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
319+
always_ff @(posedge i_clk, negedge i_nrst) begin
321320
if (i_nrst == 1'b0) begin
322321
r <= sdctrl_cmd_transmitter_r_reset;
323322
end else begin
324323
r <= rin;
325324
end
326-
end: rg_proc
325+
end
327326

328-
end: async_rst_gen
329-
else begin: no_rst_gen
327+
end: async_r_en
328+
else begin: async_r_dis
330329

331-
always_ff @(posedge i_clk) begin: rg_proc
330+
always_ff @(posedge i_clk) begin
332331
r <= rin;
333-
end: rg_proc
332+
end
334333

335-
end: no_rst_gen
334+
end: async_r_dis
336335
endgenerate
337336

338337
endmodule: sdctrl_cmd_transmitter

‎sv/rtl/internal/sdctrl/sdctrl_cmd_transmitter_pkg.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -79,5 +79,4 @@ const sdctrl_cmd_transmitter_registers sdctrl_cmd_transmitter_r_reset = '{
7979
1'b1, // cmd_dir
8080
1'b0 // wdog_ena
8181
};
82-
8382
endpackage: sdctrl_cmd_transmitter_pkg

‎sv/rtl/internal/sdctrl/sdctrl_crc16.sv‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@
1717
`timescale 1ns/10ps
1818

1919
module sdctrl_crc16 #(
20-
parameter bit async_reset = 1'b0
20+
parameter logic async_reset = 1'b0
2121
)
2222
(
2323
input logic i_clk, // CPU clock
@@ -30,7 +30,8 @@ module sdctrl_crc16 #(
3030

3131
import sdctrl_crc16_pkg::*;
3232

33-
sdctrl_crc16_registers r, rin;
33+
sdctrl_crc16_registers r;
34+
sdctrl_crc16_registers rin;
3435

3536

3637
always_comb
@@ -39,11 +40,10 @@ begin: comb_proc
3940
logic v_inv16_0;
4041
logic [15:0] vb_crc16_0;
4142

43+
v = r;
4244
v_inv16_0 = 1'b0;
4345
vb_crc16_0 = '0;
4446

45-
v = r;
46-
4747
// CRC16 = x^16 + x^12 + x^5 + 1
4848
v_inv16_0 = (r.crc16[15] ^ i_dat);
4949
vb_crc16_0[15] = r.crc16[14];
@@ -69,7 +69,7 @@ begin: comb_proc
6969
v.crc16 = vb_crc16_0;
7070
end
7171

72-
if (~async_reset && i_nrst == 1'b0) begin
72+
if ((~async_reset) && (i_nrst == 1'b0)) begin
7373
v = sdctrl_crc16_r_reset;
7474
end
7575

@@ -78,26 +78,25 @@ begin: comb_proc
7878
rin = v;
7979
end: comb_proc
8080

81-
8281
generate
83-
if (async_reset) begin: async_rst_gen
82+
if (async_reset) begin: async_r_en
8483

85-
always_ff @(posedge i_clk, negedge i_nrst) begin: rg_proc
84+
always_ff @(posedge i_clk, negedge i_nrst) begin
8685
if (i_nrst == 1'b0) begin
8786
r <= sdctrl_crc16_r_reset;
8887
end else begin
8988
r <= rin;
9089
end
91-
end: rg_proc
90+
end
9291

93-
end: async_rst_gen
94-
else begin: no_rst_gen
92+
end: async_r_en
93+
else begin: async_r_dis
9594

96-
always_ff @(posedge i_clk) begin: rg_proc
95+
always_ff @(posedge i_clk) begin
9796
r <= rin;
98-
end: rg_proc
97+
end
9998

100-
end: no_rst_gen
99+
end: async_r_dis
101100
endgenerate
102101

103102
endmodule: sdctrl_crc16

‎sv/rtl/internal/sdctrl/sdctrl_crc16_pkg.sv‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,5 +23,4 @@ typedef struct {
2323
const sdctrl_crc16_registers sdctrl_crc16_r_reset = '{
2424
'0 // crc16
2525
};
26-
2726
endpackage: sdctrl_crc16_pkg

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