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RISC-V: Adding R_RISCV_LPAD relocation type
We introduce a new relocation type[1] for landing pad, that used for linker relaxation used, the relaxation part will be a seperated patch. [1] riscv-non-isa/riscv-elf-psabi-doc#452
1 parent 75e8a97 commit 849a761

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16 files changed

+122
-3
lines changed

16 files changed

+122
-3
lines changed

‎bfd/bfd-in2.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5430,6 +5430,7 @@ enum bfd_reloc_code_real
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BFD_RELOC_RISCV_32_PCREL,
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BFD_RELOC_RISCV_SET_ULEB128,
54325432
BFD_RELOC_RISCV_SUB_ULEB128,
5433+
BFD_RELOC_RISCV_LPAD,
54335434

54345435
/* Renesas RL78 Relocations. */
54355436
BFD_RELOC_RL78_NEG8,

‎bfd/elfnn-riscv.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2785,6 +2785,7 @@ riscv_elf_relocate_section (bfd *output_bfd,
27852785
case R_RISCV_COPY:
27862786
case R_RISCV_JUMP_SLOT:
27872787
case R_RISCV_RELATIVE:
2788+
case R_RISCV_LPAD:
27882789
/* These require nothing of us at all. */
27892790
continue;
27902791

‎bfd/elfxx-riscv.c‎

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -876,7 +876,20 @@ static reloc_howto_type howto_table[] =
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false, /* partial_inplace */
877877
0, /* src_mask */
878878
ENCODE_ITYPE_IMM (-1U), /* dst_mask */
879-
false) /* pcrel_offset */
879+
false), /* pcrel_offset */
880+
HOWTO (R_RISCV_LPAD, /* type */
881+
0, /* rightshift */
882+
0, /* size */
883+
0, /* bitsize */
884+
false, /* pc_relative */
885+
0, /* bitpos */
886+
complain_overflow_dont, /* complain_on_overflow */
887+
bfd_elf_generic_reloc, /* special_function */
888+
"R_RISCV_LPAD", /* name */
889+
false, /* partial_inplace */
890+
0, /* src_mask */
891+
0, /* dst_mask */
892+
false) /* pcrel_offset */
880893
};
881894

882895
static reloc_howto_type howto_table_internal[] =
@@ -1020,6 +1033,7 @@ static const struct elf_reloc_map riscv_reloc_map[] =
10201033
{ BFD_RELOC_RISCV_32_PCREL, R_RISCV_32_PCREL },
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{ BFD_RELOC_RISCV_SET_ULEB128, R_RISCV_SET_ULEB128 },
10221035
{ BFD_RELOC_RISCV_SUB_ULEB128, R_RISCV_SUB_ULEB128 },
1036+
{ BFD_RELOC_RISCV_LPAD, R_RISCV_LPAD },
10231037
};
10241038

10251039
/* Given a BFD reloc type, return a howto structure. */

‎bfd/libbfd.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2467,6 +2467,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
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"BFD_RELOC_RISCV_32_PCREL",
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"BFD_RELOC_RISCV_SET_ULEB128",
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"BFD_RELOC_RISCV_SUB_ULEB128",
2470+
"BFD_RELOC_RISCV_LPAD",
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"BFD_RELOC_RL78_NEG8",
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"BFD_RELOC_RL78_NEG16",
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"BFD_RELOC_RL78_NEG24",

‎bfd/reloc.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5036,6 +5036,8 @@ ENUMX
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BFD_RELOC_RISCV_SET_ULEB128
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ENUMX
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BFD_RELOC_RISCV_SUB_ULEB128
5039+
ENUMX
5040+
BFD_RELOC_RISCV_LPAD
50395041
ENUMDOC
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RISC-V relocations.
50415043

‎gas/config/tc-riscv.c‎

Lines changed: 26 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1956,6 +1956,9 @@ riscv_apply_const_reloc (bfd_reloc_code_real_type reloc_type, bfd_vma value)
19561956
case BFD_RELOC_RISCV_LO12_I:
19571957
return ENCODE_ITYPE_IMM (value);
19581958

1959+
case BFD_RELOC_RISCV_LPAD:
1960+
return ENCODE_UTYPE_IMM (value << RISCV_IMM_BITS);
1961+
19591962
default:
19601963
abort ();
19611964
}
@@ -3678,6 +3681,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
36783681
*imm_reloc = BFD_RELOC_RISCV_HI20;
36793682
imm_expr->X_add_number <<= RISCV_IMM_BITS;
36803683
}
3684+
{
3685+
bool is_lpad = strcmp (str, "lpad") == 0;
3686+
if (is_lpad)
3687+
{
3688+
/* Always insert a lpad relocation for lpad instruction. */
3689+
*imm_reloc = BFD_RELOC_RISCV_LPAD;
3690+
/* And recover the immediate format to unshift value. */
3691+
imm_expr->X_add_number >>= RISCV_IMM_BITS;
3692+
}
3693+
}
36813694
asarg = expr_parse_end;
36823695
continue;
36833696

@@ -4671,6 +4684,14 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg)
46714684

46724685
switch (fixP->fx_r_type)
46734686
{
4687+
case BFD_RELOC_RISCV_LPAD:
4688+
bfd_putl32 (riscv_apply_const_reloc (fixP->fx_r_type, *valP)
4689+
| bfd_getl32 (buf), buf);
4690+
fixP->fx_done = false;
4691+
fixP->fx_addnumber = 0;
4692+
fixP->fx_offset = 0;
4693+
relaxable = true;
4694+
break;
46744695
case BFD_RELOC_RISCV_HI20:
46754696
case BFD_RELOC_RISCV_LO12_I:
46764697
case BFD_RELOC_RISCV_LO12_S:
@@ -4965,8 +4986,11 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg)
49654986
if (fixP->fx_subsy != NULL)
49664987
as_bad_subtract (fixP);
49674988

4968-
/* Add an R_RISCV_RELAX reloc if the reloc is relaxable. */
4969-
if (relaxable && fixP->fx_tcbit && fixP->fx_addsy != NULL)
4989+
/* Add an R_RISCV_RELAX reloc if the reloc is relaxable,
4990+
and we need that for R_RISCV_LPAD as well. */
4991+
if (relaxable && fixP->fx_tcbit
4992+
&& (fixP->fx_addsy != NULL
4993+
|| (fixP->fx_r_type == BFD_RELOC_RISCV_LPAD)))
49704994
{
49714995
fixP->fx_next = xmemdup (fixP, sizeof (*fixP), sizeof (*fixP));
49724996
fixP->fx_next->fx_addsy = fixP->fx_next->fx_subsy = NULL;

‎gas/testsuite/gas/riscv/lpad_reloc-norelax.d‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
#as: -march=rv64izicfilp -mno-relax
2+
#source: lpad_reloc.s
3+
#objdump: -dr
4+
5+
.*:[ ]+file format .*
6+
7+
8+
Disassembly of section .text:
9+
10+
0+000 <foo>:
11+
[ ]+0:[ ]+00000017[ ]+lpad[ ]+0x0
12+
[ ]+0:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
13+
[ ]+4:[ ]+00001017[ ]+lpad[ ]+0x1
14+
[ ]+4:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
15+
[ ]+8:[ ]+00064017[ ]+lpad[ ]+0x64
16+
[ ]+8:[ ]+R_RISCV_LPAD[ ]+\*ABS\*

‎gas/testsuite/gas/riscv/lpad_reloc.d‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
#as: -march=rv64izicfilp
2+
#source: lpad_reloc.s
3+
#objdump: -dr
4+
5+
.*:[ ]+file format .*
6+
7+
8+
Disassembly of section .text:
9+
10+
0+000 <foo>:
11+
[ ]+0:[ ]+00000017[ ]+lpad[ ]+0x0
12+
[ ]+0:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
13+
[ ]+0:[ ]+R_RISCV_RELAX[ ]+\*ABS\*
14+
[ ]+4:[ ]+00001017[ ]+lpad[ ]+0x1
15+
[ ]+4:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
16+
[ ]+4:[ ]+R_RISCV_RELAX[ ]+\*ABS\*
17+
[ ]+8:[ ]+00064017[ ]+lpad[ ]+0x64
18+
[ ]+8:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
19+
[ ]+8:[ ]+R_RISCV_RELAX[ ]+\*ABS\*

‎gas/testsuite/gas/riscv/lpad_reloc.s‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
foo:
2+
lpad 0
3+
lpad 1
4+
lpad 100

‎gas/testsuite/gas/riscv/zicfisslp-32.d‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,3 +25,5 @@ Disassembly of section .text:
2525
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
2626
[ ]+[0-9a-f]+:[ ]+6281[ ]+sspopchk[ ]+t0
2727
[ ]+[0-9a-f]+:[ ]+00111017[ ]+lpad[ ]+0x111
28+
[ ]+[0-9a-f]+:[ ]+R_RISCV_LPAD[ ]+\*ABS\*
29+
[ ]+[0-9a-f]+:[ ]+R_RISCV_RELAX[ ]+\*ABS\*

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