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RISC-V: Add intrinsics testcases for SiFive Xsfvcp extensions.
1 parent c646364 commit 865eb47

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‎gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_fv.c‎

Lines changed: 189 additions & 0 deletions
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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typedef _Float16 float16_t;
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typedef float float32_t;
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typedef double float64_t;
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/*
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** test_sf_vc_fv_se_u16mf4:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16mf4(const int bit_field26, const int bit_field11_7, vuint16mf4_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16mf4(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u16mf2:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16mf2(const int bit_field26, const int bit_field11_7, vuint16mf2_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16mf2(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u16m1:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16m1(const int bit_field26, const int bit_field11_7, vuint16m1_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16m1(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u16m2:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16m2(const int bit_field26, const int bit_field11_7, vuint16m2_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16m2(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u16m4:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16m4(const int bit_field26, const int bit_field11_7, vuint16m4_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16m4(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u16m8:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u16m8(const int bit_field26, const int bit_field11_7, vuint16m8_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u16m8(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u32mf2:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u32mf2(const int bit_field26, const int bit_field11_7, vuint32mf2_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u32mf2(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u32m1:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u32m1(const int bit_field26, const int bit_field11_7, vuint32m1_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u32m1(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u32m2:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u32m2(const int bit_field26, const int bit_field11_7, vuint32m2_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u32m2(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u32m4:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u32m4(const int bit_field26, const int bit_field11_7, vuint32m4_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u32m4(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u32m8:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u32m8(const int bit_field26, const int bit_field11_7, vuint32m8_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u32m8(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u64m1:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u64m1(const int bit_field26, const int bit_field11_7, vuint64m1_t vs2, float64_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u64m1(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u64m2:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u64m2(const int bit_field26, const int bit_field11_7, vuint64m2_t vs2, float64_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u64m2(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u64m4:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u64m4(const int bit_field26, const int bit_field11_7, vuint64m4_t vs2, float64_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u64m4(bit_field26, bit_field11_7, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fv_se_u64m8:
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** ...
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** sf\.vc\.fv\t[0-9]+,[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fv_se_u64m8(const int bit_field26, const int bit_field11_7, vuint64m8_t vs2, float64_t fs1, size_t vl)
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{
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__riscv_sf_vc_fv_se_u64m8(bit_field26, bit_field11_7, vs2, fs1, vl);
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}

‎gcc/testsuite/gcc.target/riscv/rvv/xsfvector/sf_vc_fvv.c‎

Lines changed: 190 additions & 0 deletions
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv_xsfvcp -mabi=lp64d -O3" } */
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/* { dg-final { check-function-bodies "**" "" } } */
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#include "riscv_vector.h"
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typedef _Float16 float16_t;
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typedef float float32_t;
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typedef double float64_t;
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/*
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** test_sf_vc_fvv_se_u16mf4:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16mf4(const int bit_field26, vuint16mf4_t vd, vuint16mf4_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fvv_se_u16mf4(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u16mf2:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16mf2(const int bit_field26, vuint16mf2_t vd, vuint16mf2_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fvv_se_u16mf2(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u16m1:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16m1(const int bit_field26, vuint16m1_t vd, vuint16m1_t vs2, float16_t fs1, size_t vl)
44+
{
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__riscv_sf_vc_fvv_se_u16m1(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u16m2:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16m2(const int bit_field26, vuint16m2_t vd, vuint16m2_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fvv_se_u16m2(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u16m4:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16m4(const int bit_field26, vuint16m4_t vd, vuint16m4_t vs2, float16_t fs1, size_t vl)
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{
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__riscv_sf_vc_fvv_se_u16m4(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u16m8:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u16m8(const int bit_field26, vuint16m8_t vd, vuint16m8_t vs2, float16_t fs1, size_t vl)
80+
{
81+
__riscv_sf_vc_fvv_se_u16m8(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u32mf2:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u32mf2(const int bit_field26, vuint32mf2_t vd, vuint32mf2_t vs2, float32_t fs1, size_t vl)
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{
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__riscv_sf_vc_fvv_se_u32mf2(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u32m1:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u32m1(const int bit_field26, vuint32m1_t vd, vuint32m1_t vs2, float32_t fs1, size_t vl)
104+
{
105+
__riscv_sf_vc_fvv_se_u32m1(bit_field26, vd, vs2, fs1, vl);
106+
}
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/*
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** test_sf_vc_fvv_se_u32m2:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u32m2(const int bit_field26, vuint32m2_t vd, vuint32m2_t vs2, float32_t fs1, size_t vl)
116+
{
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__riscv_sf_vc_fvv_se_u32m2(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u32m4:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u32m4(const int bit_field26, vuint32m4_t vd, vuint32m4_t vs2, float32_t fs1, size_t vl)
128+
{
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__riscv_sf_vc_fvv_se_u32m4(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u32m8:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u32m8(const int bit_field26, vuint32m8_t vd, vuint32m8_t vs2, float32_t fs1, size_t vl)
140+
{
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__riscv_sf_vc_fvv_se_u32m8(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u64m1:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u64m1(const int bit_field26, vuint64m1_t vd, vuint64m1_t vs2, float64_t fs1, size_t vl)
152+
{
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__riscv_sf_vc_fvv_se_u64m1(bit_field26, vd, vs2, fs1, vl);
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}
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/*
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** test_sf_vc_fvv_se_u64m2:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u64m2(const int bit_field26, vuint64m2_t vd, vuint64m2_t vs2, float64_t fs1, size_t vl)
164+
{
165+
__riscv_sf_vc_fvv_se_u64m2(bit_field26, vd, vs2, fs1, vl);
166+
}
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/*
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** test_sf_vc_fvv_se_u64m4:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u64m4(const int bit_field26, vuint64m4_t vd, vuint64m4_t vs2, float64_t fs1, size_t vl)
176+
{
177+
__riscv_sf_vc_fvv_se_u64m4(bit_field26, vd, vs2, fs1, vl);
178+
}
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/*
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** test_sf_vc_fvv_se_u64m8:
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** ...
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** sf\.vc\.fvv\t[0-9]+,v[0-9]+,v[0-9]+,fa[0-9]+
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** ...
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*/
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void test_sf_vc_fvv_se_u64m8(const int bit_field26, vuint64m8_t vd, vuint64m8_t vs2, float64_t fs1, size_t vl)
188+
{
189+
__riscv_sf_vc_fvv_se_u64m8(bit_field26, vd, vs2, fs1, vl);
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}

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