RISC-V: Add intrinsics support for SiFive Xsfvcp extensions.

Author: yulong18

gcc/config/riscv/constraints.md

@@ -295,3 +295,13 @@
   "Shifting immediate for SIMD shufflei3."
   (and (match_code "const_int")
        (match_test "IN_RANGE (ival, -64, -1)")))
+
+(define_constraint "B"
+  "A 2-bit unsigned immediate for CSR access instructions."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 0, 3)")))
+
+(define_constraint "O"
+  "A 1-bit unsigned immediate for CSR access instructions."
+  (and (match_code "const_int")
+       (match_test "IN_RANGE (ival, 0, 1)")))

gcc/config/riscv/generic-vector-ooo.md

@@ -141,3 +141,7 @@
   (eq_attr "type" "rdvlenb,rdvl")
   "vxu_ooo_issue,vxu_ooo_issue")
 
+;; Vector sf_vcp.
+(define_insn_reservation "vec_sf_vcp" 2
+  (eq_attr "type" "sf_vc,sf_vc_se")
+  "vxu_ooo_issue")

gcc/config/riscv/genrvv-type-indexer.cc

@@ -290,6 +290,8 @@ main (int argc, const char **argv)
 	fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ %s,\n", eew,
 		 inttype (eew, LMUL1_LOG2, /* unsigned_p */true).c_str ());
 
+      fprintf (fp, "  /*X2*/ INVALID,\n");
+
       for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
 	{
 	  unsigned multiple_of_lmul = 1 << lmul_log2_offset;
@@ -411,6 +413,9 @@ main (int argc, const char **argv)
 	      fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
 		       eew);
 
+	    fprintf (fp, "  /*X2*/ %s,\n",
+		     inttype (sew * 2, lmul_log2 + 1, /*unsigned_p*/ true).c_str ());
+
 	    for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
 	      {
 		unsigned multiple_of_lmul = 1 << lmul_log2_offset;
@@ -485,6 +490,8 @@ main (int argc, const char **argv)
 	for (unsigned eew : EEW_SIZE_LIST)
 	  fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n", eew);
 
+	fprintf (fp, "  /*X2*/ INVALID,\n");
+
 	for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
 	  {
 	    unsigned multiple_of_lmul = 1 << lmul_log2_offset;
@@ -571,6 +578,8 @@ main (int argc, const char **argv)
 	    fprintf (fp, "  /*UNSIGNED_EEW%d_LMUL1_INTERPRET*/ INVALID,\n",
 		     eew);
 
+	  fprintf (fp, "  /*X2*/ INVALID,\n");
+
 	  for (unsigned lmul_log2_offset : {1, 2, 3, 4, 5, 6})
 	    {
 	      unsigned multiple_of_lmul = 1 << lmul_log2_offset;

gcc/config/riscv/riscv-vector-builtins-shapes.cc

@@ -1343,6 +1343,51 @@ struct sf_vfnrclip_def : public build_base
   }
 };
 
+/* sf_vcix_se_def class.  */
+struct sf_vcix_se_def : public build_base
+{
+  const char *get_name (function_builder &b, const function_instance &instance,
+		  bool overloaded_p) const override
+  {
+    /* Return nullptr if it can not be overloaded.  */
+    if (overloaded_p)
+      return nullptr;
+
+    b.append_base_name (instance.base_name);
+
+    /* vop --> vop<op>_se_<type>.  */
+    if (!overloaded_p)
+      {
+	b.append_name (operand_suffixes[instance.op_info->op]);
+	b.append_name ("_se");
+	b.append_name (type_suffixes[instance.type.index].vector);
+      }
+    return b.finish_name ();
+  }
+};
+
+/* sf_vcix_def class.  */
+struct sf_vcix_def : public build_base
+{
+  const char *get_name (function_builder &b, const function_instance &instance,
+		  bool overloaded_p) const override
+  {
+    /* Return nullptr if it can not be overloaded.  */
+    if (overloaded_p)
+      return nullptr;
+
+    b.append_base_name (instance.base_name);
+
+    /* vop --> vop_<type>.  */
+    if (!overloaded_p)
+      {
+	b.append_name (operand_suffixes[instance.op_info->op]);
+	b.append_name (type_suffixes[instance.type.index].vector);
+      }
+    return b.finish_name ();
+  }
+};
+
 SHAPE(vsetvl, vsetvl)
 SHAPE(vsetvl, vsetvlmax)
 SHAPE(loadstore, loadstore)
@@ -1379,4 +1424,6 @@ SHAPE(crypto_vi, crypto_vi)
 SHAPE(crypto_vv_no_op_type, crypto_vv_no_op_type)
 SHAPE (sf_vqmacc, sf_vqmacc)
 SHAPE (sf_vfnrclip, sf_vfnrclip)
+SHAPE(sf_vcix_se, sf_vcix_se)
+SHAPE(sf_vcix, sf_vcix)
 } // end namespace riscv_vector

gcc/config/riscv/riscv-vector-builtins-shapes.h

@@ -62,6 +62,8 @@ extern const function_shape *const crypto_vv_no_op_type;
 /* Sifive vendor extension.  */
 extern const function_shape *const sf_vqmacc;
 extern const function_shape *const sf_vfnrclip;
+extern const function_shape *const sf_vcix_se;
+extern const function_shape *const sf_vcix;
 }
 
 } // end namespace riscv_vector

gcc/config/riscv/riscv-vector-builtins-types.def

@@ -363,6 +363,18 @@ along with GCC; see the file COPYING3. If not see
 #define DEF_RVV_QMACC_OPS(TYPE, REQUIRE)
 #endif
 
+/* Use "DEF_RVV_X2_U_OPS" macro include unsigned integer which will
+   be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_X2_U_OPS
+#define DEF_RVV_X2_U_OPS(TYPE, REQUIRE)
+#endif
+
+/* Use "DEF_RVV_X2_WU_OPS" macro include widen unsigned integer which will
+   be iterated and registered as intrinsic functions.  */
+#ifndef DEF_RVV_X2_WU_OPS
+#define DEF_RVV_X2_WU_OPS(TYPE, REQUIRE)
+#endif
+
 DEF_RVV_I_OPS (vint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
 DEF_RVV_I_OPS (vint8mf4_t, 0)
 DEF_RVV_I_OPS (vint8mf2_t, 0)
@@ -1451,6 +1463,32 @@ DEF_RVV_QMACC_OPS (vint32m2_t, 0)
 DEF_RVV_QMACC_OPS (vint32m4_t, 0)
 DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 
+DEF_RVV_X2_U_OPS (vuint8mf8_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_U_OPS (vuint8mf4_t, 0)
+DEF_RVV_X2_U_OPS (vuint8mf2_t, 0)
+DEF_RVV_X2_U_OPS (vuint8m1_t, 0)
+DEF_RVV_X2_U_OPS (vuint8m2_t, 0)
+DEF_RVV_X2_U_OPS (vuint8m4_t, 0)
+DEF_RVV_X2_U_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_U_OPS (vuint16mf2_t, 0)
+DEF_RVV_X2_U_OPS (vuint16m1_t, 0)
+DEF_RVV_X2_U_OPS (vuint16m2_t, 0)
+DEF_RVV_X2_U_OPS (vuint16m4_t, 0)
+DEF_RVV_X2_U_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_U_OPS (vuint32m1_t, 0)
+DEF_RVV_X2_U_OPS (vuint32m2_t, 0)
+DEF_RVV_X2_U_OPS (vuint32m4_t, 0)
+
+DEF_RVV_X2_WU_OPS (vuint16mf4_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_WU_OPS (vuint16mf2_t, 0)
+DEF_RVV_X2_WU_OPS (vuint16m1_t, 0)
+DEF_RVV_X2_WU_OPS (vuint16m2_t, 0)
+DEF_RVV_X2_WU_OPS (vuint16m4_t, 0)
+DEF_RVV_X2_WU_OPS (vuint32mf2_t, RVV_REQUIRE_MIN_VLEN_64)
+DEF_RVV_X2_WU_OPS (vuint32m1_t, 0)
+DEF_RVV_X2_WU_OPS (vuint32m2_t, 0)
+DEF_RVV_X2_WU_OPS (vuint32m4_t, 0)
+
 #undef DEF_RVV_I_OPS
 #undef DEF_RVV_U_OPS
 #undef DEF_RVV_F_OPS
@@ -1506,3 +1544,5 @@ DEF_RVV_QMACC_OPS (vint32m8_t, 0)
 #undef DEF_RVV_CRYPTO_SEW64_OPS
 #undef DEF_RVV_F32_OPS
 #undef DEF_RVV_QMACC_OPS
+#undef DEF_RVV_X2_U_OPS
+#undef DEF_RVV_X2_WU_OPS