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aarch64: Add support for SME_F16F16
This patch adds support for the SME_F16F16 extension. The extension adds two new instructions to convert from a single vector of f16s to two vectors of f32s. It also adds f16 variants of existing SME ZA instructions. gcc/ * config/aarch64/aarch64-option-extensions.def (sme-f16f16): New extension. * doc/invoke.texi: Document it. Also document that sme-i16i64 and sme-f64f64 enable SME. * config/aarch64/aarch64.h (TARGET_STREAMING_SME_F16F16): New macro. * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Conditionally define __ARM_FEATURE_SME_F16F16. * config/aarch64/aarch64-sve-builtins-sve2.def (svcvt, svcvtl): Add new SME_F16F16 intrinsics. * config/aarch64/aarch64-sve-builtins-sme.def: Add SME_F16F16 forms of existing intrinsics. * config/aarch64/aarch64-sve-builtins.cc (TYPES_h_float) (TYPES_cvt_f32_f16, TYPES_za_h_float): New type macros. * config/aarch64/aarch64-sve-builtins-base.cc (svcvt_impl::expand): Add sext_optab as another possibility. * config/aarch64/aarch64-sve-builtins-sve2.h (svcvtl): Declare. * config/aarch64/aarch64-sve-builtins-sve2.cc (svcvtl_impl): New class. (svcvtl): New function. * config/aarch64/iterators.md (VNx8SF_ONLY): New mode iterator. (SME_ZA_SDFx24): Replace with... (SME_ZA_HSDFx24): ...this. (SME_MOP_SDF): Replace with... (SME_MOP_HSDF): ...this. (SME_BINARY_SLICE_SDF): Replace with... (SME_BINARY_SLICE_HSDF): ...this. * config/aarch64/aarch64-sve2.md (extendvnx8hfvnx8sf2) (@aarch64_sve_cvtl<mode>): New patterns. * config/aarch64/aarch64-sme.md (@aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>): Extend to... (@aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>): ...this. (*aarch64_sme_<SME_BINARY_SLICE_SDF:optab><mode>_plus): Extend to... (*aarch64_sme_<SME_BINARY_SLICE_HSDF:optab><mode>_plus): ...this. (@aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>): Extend to HF modes. (*aarch64_sme_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus) (@aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>) (*aarch64_sme_single_<SME_FP_TERNARY_SLICE:optab><mode><mode>_plus) (@aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>) (*aarch64_sme_lane_<SME_FP_TERNARY_SLICE:optab><mode><mode>) (@aarch64_sme_<SME_FP_MOP:optab><mode><mode>): Likewise. gcc/testsuite/ * lib/target-supports.exp: Test the assembler for sve-f16f16 support. * gcc.target/aarch64/pragma_cpp_predefs_4.c: Add tests for __ARM_FEATURE_SME_F16F16. Also extend the existing SME tests. * gcc.target/aarch64/sve/acle/asm/test_sve_acle.h (TEST_X2_WIDE): New macro * gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x2.c: New test. * gcc.target/aarch64/sme2/acle-asm/add_za16_f16_vg1x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/cvt_f32_f16_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/cvtl_f32_f16_x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mla_lane_za16_f16_vg1x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mla_za16_f16_vg1x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mls_lane_za16_f16_vg1x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mls_za16_f16_vg1x4.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mopa_za16_f16.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/mops_za16_f16.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x2.c: Likewise. * gcc.target/aarch64/sme2/acle-asm/sub_za16_f16_vg1x4.c: Likewise.
1 parent 648fc67 commit e6751e1

32 files changed

+2067
-59
lines changed

‎gcc/config/aarch64/aarch64-c.cc‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
271271

272272
aarch64_def_or_undef (TARGET_SME, "__ARM_FEATURE_SME", pfile);
273273
aarch64_def_or_undef (TARGET_SME_I16I64, "__ARM_FEATURE_SME_I16I64", pfile);
274+
aarch64_def_or_undef (AARCH64_HAVE_ISA (SME_F16F16),
275+
"__ARM_FEATURE_SME_F16F16", pfile);
274276
aarch64_def_or_undef (TARGET_SME_F64F64, "__ARM_FEATURE_SME_F64F64", pfile);
275277
aarch64_def_or_undef (TARGET_SME2, "__ARM_FEATURE_SME2", pfile);
276278

‎gcc/config/aarch64/aarch64-option-extensions.def‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -225,6 +225,8 @@ AARCH64_FMV_FEATURE("sme-i16i64", SME_I64, (SME_I16I64))
225225

226226
AARCH64_OPT_FMV_EXTENSION("sme2", SME2, (SME), (), (), "sme2")
227227

228+
AARCH64_OPT_EXTENSION("sme-f16f16", SME_F16F16, (SME2), (), (), "")
229+
228230
AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
229231

230232
AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")

‎gcc/config/aarch64/aarch64-sme.md‎

Lines changed: 52 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -926,6 +926,9 @@
926926
;; -------------------------------------------------------------------------
927927
;; Includes:
928928
;; - ADD
929+
;; - FADD
930+
;; - FSUB
931+
;; - SUB
929932
;; -------------------------------------------------------------------------
930933

931934
(define_insn "@aarch64_sme_<optab><mode>"
@@ -954,26 +957,26 @@
954957
)
955958

956959
(define_insn "@aarch64_sme_<optab><mode>"
957-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
958-
(unspec:SME_ZA_SDFx24
959-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
960+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
961+
(unspec:SME_ZA_HSDFx24
962+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
960963
(reg:DI SME_STATE_REGNUM)
961964
(match_operand:SI 0 "register_operand" "Uci")
962-
(match_operand:SME_ZA_SDFx24 1 "aligned_register_operand" "Uw<vector_count>")]
963-
SME_BINARY_SLICE_SDF))]
965+
(match_operand:SME_ZA_HSDFx24 1 "aligned_register_operand" "Uw<vector_count>")]
966+
SME_BINARY_SLICE_HSDF))]
964967
"TARGET_STREAMING_SME2"
965968
"<optab>\tza.<Vetype>[%w0, 0, vgx<vector_count>], %1"
966969
)
967970

968971
(define_insn "*aarch64_sme_<optab><mode>_plus"
969-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
970-
(unspec:SME_ZA_SDFx24
971-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
972+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
973+
(unspec:SME_ZA_HSDFx24
974+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
972975
(reg:DI SME_STATE_REGNUM)
973976
(plus:SI (match_operand:SI 0 "register_operand" "Uci")
974977
(match_operand:SI 1 "const_0_to_7_operand"))
975-
(match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")]
976-
SME_BINARY_SLICE_SDF))]
978+
(match_operand:SME_ZA_HSDFx24 2 "aligned_register_operand" "Uw<vector_count>")]
979+
SME_BINARY_SLICE_HSDF))]
977980
"TARGET_STREAMING_SME2"
978981
"<optab>\tza.<Vetype>[%w0, %1, vgx<vector_count>], %2"
979982
)
@@ -1634,70 +1637,70 @@
16341637
;; -------------------------------------------------------------------------
16351638

16361639
(define_insn "@aarch64_sme_<optab><mode><mode>"
1637-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1638-
(unspec:SME_ZA_SDFx24
1639-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1640+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1641+
(unspec:SME_ZA_HSDFx24
1642+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
16401643
(reg:DI SME_STATE_REGNUM)
16411644
(match_operand:SI 0 "register_operand" "Uci")
1642-
(match_operand:SME_ZA_SDFx24 1 "aligned_register_operand" "Uw<vector_count>")
1643-
(match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")]
1645+
(match_operand:SME_ZA_HSDFx24 1 "aligned_register_operand" "Uw<vector_count>")
1646+
(match_operand:SME_ZA_HSDFx24 2 "aligned_register_operand" "Uw<vector_count>")]
16441647
SME_FP_TERNARY_SLICE))]
16451648
"TARGET_STREAMING_SME2"
16461649
"<optab>\tza.<Vetype>[%w0, 0, vgx<vector_count>], %1, %2"
16471650
)
16481651

16491652
(define_insn "*aarch64_sme_<optab><mode><mode>_plus"
1650-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1651-
(unspec:SME_ZA_SDFx24
1652-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1653+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1654+
(unspec:SME_ZA_HSDFx24
1655+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
16531656
(reg:DI SME_STATE_REGNUM)
16541657
(plus:SI (match_operand:SI 0 "register_operand" "Uci")
16551658
(match_operand:SI 1 "const_0_to_7_operand"))
1656-
(match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")
1657-
(match_operand:SME_ZA_SDFx24 3 "aligned_register_operand" "Uw<vector_count>")]
1659+
(match_operand:SME_ZA_HSDFx24 2 "aligned_register_operand" "Uw<vector_count>")
1660+
(match_operand:SME_ZA_HSDFx24 3 "aligned_register_operand" "Uw<vector_count>")]
16581661
SME_FP_TERNARY_SLICE))]
16591662
"TARGET_STREAMING_SME2"
16601663
"<optab>\tza.<Vetype>[%w0, %1, vgx<vector_count>], %2, %3"
16611664
)
16621665

16631666
(define_insn "@aarch64_sme_single_<optab><mode><mode>"
1664-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1665-
(unspec:SME_ZA_SDFx24
1666-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1667+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1668+
(unspec:SME_ZA_HSDFx24
1669+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
16671670
(reg:DI SME_STATE_REGNUM)
16681671
(match_operand:SI 0 "register_operand" "Uci")
1669-
(match_operand:SME_ZA_SDFx24 1 "register_operand" "w")
1670-
(vec_duplicate:SME_ZA_SDFx24
1671-
(match_operand:<VSINGLE> 2 "register_operand" "x"))]
1672+
(match_operand:SME_ZA_HSDFx24 1 "register_operand" "w")
1673+
(vec_duplicate:SME_ZA_HSDFx24
1674+
(match_operand:<SME_ZA_HSDFx24:VSINGLE> 2 "register_operand" "x"))]
16721675
SME_FP_TERNARY_SLICE))]
16731676
"TARGET_STREAMING_SME2"
16741677
"<optab>\tza.<Vetype>[%w0, 0, vgx<vector_count>], %1, %2.<Vetype>"
16751678
)
16761679

16771680
(define_insn "*aarch64_sme_single_<optab><mode><mode>_plus"
1678-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1679-
(unspec:SME_ZA_SDFx24
1680-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1681+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1682+
(unspec:SME_ZA_HSDFx24
1683+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
16811684
(reg:DI SME_STATE_REGNUM)
16821685
(plus:SI (match_operand:SI 0 "register_operand" "Uci")
16831686
(match_operand:SI 1 "const_0_to_7_operand"))
1684-
(match_operand:SME_ZA_SDFx24 2 "register_operand" "w")
1685-
(vec_duplicate:SME_ZA_SDFx24
1686-
(match_operand:<VSINGLE> 3 "register_operand" "x"))]
1687+
(match_operand:SME_ZA_HSDFx24 2 "register_operand" "w")
1688+
(vec_duplicate:SME_ZA_HSDFx24
1689+
(match_operand:<SME_ZA_HSDFx24:VSINGLE> 3 "register_operand" "x"))]
16871690
SME_FP_TERNARY_SLICE))]
16881691
"TARGET_STREAMING_SME2"
16891692
"<optab>\tza.<Vetype>[%w0, %1, vgx<vector_count>], %2, %3.<Vetype>"
16901693
)
16911694

16921695
(define_insn "@aarch64_sme_lane_<optab><mode><mode>"
1693-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1694-
(unspec:SME_ZA_SDFx24
1695-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1696+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1697+
(unspec:SME_ZA_HSDFx24
1698+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
16961699
(reg:DI SME_STATE_REGNUM)
16971700
(match_operand:SI 0 "register_operand" "Uci")
1698-
(match_operand:SME_ZA_SDFx24 1 "aligned_register_operand" "Uw<vector_count>")
1699-
(unspec:SME_ZA_SDFx24
1700-
[(match_operand:<VSINGLE> 2 "register_operand" "x")
1701+
(match_operand:SME_ZA_HSDFx24 1 "aligned_register_operand" "Uw<vector_count>")
1702+
(unspec:SME_ZA_HSDFx24
1703+
[(match_operand:<SME_ZA_HSDFx24:VSINGLE> 2 "register_operand" "x")
17011704
(match_operand:SI 3 "const_int_operand")]
17021705
UNSPEC_SVE_LANE_SELECT)]
17031706
SME_FP_TERNARY_SLICE))]
@@ -1706,15 +1709,15 @@
17061709
)
17071710

17081711
(define_insn "*aarch64_sme_lane_<optab><mode><mode>"
1709-
[(set (reg:SME_ZA_SDFx24 ZA_REGNUM)
1710-
(unspec:SME_ZA_SDFx24
1711-
[(reg:SME_ZA_SDFx24 ZA_REGNUM)
1712+
[(set (reg:SME_ZA_HSDFx24 ZA_REGNUM)
1713+
(unspec:SME_ZA_HSDFx24
1714+
[(reg:SME_ZA_HSDFx24 ZA_REGNUM)
17121715
(reg:DI SME_STATE_REGNUM)
17131716
(plus:SI (match_operand:SI 0 "register_operand" "Uci")
17141717
(match_operand:SI 1 "const_0_to_7_operand"))
1715-
(match_operand:SME_ZA_SDFx24 2 "aligned_register_operand" "Uw<vector_count>")
1716-
(unspec:SME_ZA_SDFx24
1717-
[(match_operand:<VSINGLE> 3 "register_operand" "x")
1718+
(match_operand:SME_ZA_HSDFx24 2 "aligned_register_operand" "Uw<vector_count>")
1719+
(unspec:SME_ZA_HSDFx24
1720+
[(match_operand:<SME_ZA_HSDFx24:VSINGLE> 3 "register_operand" "x")
17181721
(match_operand:SI 4 "const_int_operand")]
17191722
UNSPEC_SVE_LANE_SELECT)]
17201723
SME_FP_TERNARY_SLICE))]
@@ -1871,15 +1874,15 @@
18711874
;; -------------------------------------------------------------------------
18721875

18731876
(define_insn "@aarch64_sme_<optab><mode><mode>"
1874-
[(set (reg:SME_MOP_SDF ZA_REGNUM)
1875-
(unspec:SME_MOP_SDF
1876-
[(reg:SME_MOP_SDF ZA_REGNUM)
1877+
[(set (reg:SME_MOP_HSDF ZA_REGNUM)
1878+
(unspec:SME_MOP_HSDF
1879+
[(reg:SME_MOP_HSDF ZA_REGNUM)
18771880
(reg:DI SME_STATE_REGNUM)
18781881
(match_operand:DI 0 "const_int_operand")
18791882
(match_operand:<VPRED> 1 "register_operand" "Upl")
18801883
(match_operand:<VPRED> 2 "register_operand" "Upl")
1881-
(match_operand:SME_MOP_SDF 3 "register_operand" "w")
1882-
(match_operand:SME_MOP_SDF 4 "register_operand" "w")]
1884+
(match_operand:SME_MOP_HSDF 3 "register_operand" "w")
1885+
(match_operand:SME_MOP_HSDF 4 "register_operand" "w")]
18831886
SME_FP_MOP))]
18841887
"TARGET_STREAMING"
18851888
"<b><optab>\tza%0.<Vetype>, %1/m, %2/m, %3.<Vetype>, %4.<Vetype>"

‎gcc/config/aarch64/aarch64-sve-builtins-base.cc‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -684,8 +684,11 @@ class svcvt_impl : public function_base
684684
optab = e.type_suffix (0).unsigned_p ? ufix_optab : sfix_optab;
685685
else if (e.type_suffix (1).integer_p)
686686
optab = e.type_suffix (1).unsigned_p ? ufloat_optab : sfloat_optab;
687-
else
687+
else if (e.type_suffix (0).element_bits
688+
< e.type_suffix (1).element_bits)
688689
optab = trunc_optab;
690+
else
691+
optab = sext_optab;
689692
icode = convert_optab_handler (optab, mode0, mode1);
690693
gcc_assert (icode != CODE_FOR_nothing);
691694
return e.use_exact_insn (icode);

‎gcc/config/aarch64/aarch64-sve-builtins-sme.def‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,21 @@ DEF_SME_ZA_FUNCTION_GS (svmls_lane, binary_za_slice_lane, za_d_float,
206206
DEF_SME_ZA_FUNCTION_GS (svsub, unary_za_slice, za_d_float, vg1x24, none)
207207
#undef REQUIRED_EXTENSIONS
208208

209+
#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F16F16)
210+
DEF_SME_ZA_FUNCTION_GS (svadd, unary_za_slice, za_h_float, vg1x24, none)
211+
DEF_SME_ZA_FUNCTION_GS (svmla, binary_za_slice_opt_single, za_h_float,
212+
vg1x24, none)
213+
DEF_SME_ZA_FUNCTION_GS (svmla_lane, binary_za_slice_lane, za_h_float,
214+
vg1x24, none)
215+
DEF_SME_ZA_FUNCTION_GS (svmls, binary_za_slice_opt_single, za_h_float,
216+
vg1x24, none)
217+
DEF_SME_ZA_FUNCTION_GS (svmls_lane, binary_za_slice_lane, za_h_float,
218+
vg1x24, none)
219+
DEF_SME_ZA_FUNCTION (svmopa, binary_za_m, za_h_float, za_m)
220+
DEF_SME_ZA_FUNCTION (svmops, binary_za_m, za_h_float, za_m)
221+
DEF_SME_ZA_FUNCTION_GS (svsub, unary_za_slice, za_h_float, vg1x24, none)
222+
#undef REQUIRED_EXTENSIONS
223+
209224
#undef DEF_SME_ZA_FUNCTION
210225
#undef DEF_SME_ZA_FUNCTION_GS
211226
#undef DEF_SME_FUNCTION

‎gcc/config/aarch64/aarch64-sve-builtins-sve2.cc‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,6 +211,16 @@ class svclamp_impl : public function_base
211211
}
212212
};
213213

214+
class svcvtl_impl : public function_base
215+
{
216+
public:
217+
rtx
218+
expand (function_expander &e) const override
219+
{
220+
return e.use_exact_insn (code_for_aarch64_sve_cvtl (e.result_mode ()));
221+
}
222+
};
223+
214224
class svcvtn_impl : public function_base
215225
{
216226
public:
@@ -908,6 +918,7 @@ FUNCTION (svcdot, svcdot_impl,)
908918
FUNCTION (svcdot_lane, svcdot_lane_impl,)
909919
FUNCTION (svclamp, svclamp_impl,)
910920
FUNCTION (svcvtlt, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTLT))
921+
FUNCTION (svcvtl, svcvtl_impl,)
911922
FUNCTION (svcvtn, svcvtn_impl,)
912923
FUNCTION (svcvtx, unspec_based_function, (-1, -1, UNSPEC_COND_FCVTX))
913924
FUNCTION (svcvtxnt, CODE_FOR_MODE1 (aarch64_sve2_cvtxnt),)

‎gcc/config/aarch64/aarch64-sve-builtins-sve2.def‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,11 @@ DEF_SVE_FUNCTION (svamax, binary_opt_single_n, all_float, mxz)
336336
DEF_SVE_FUNCTION (svamin, binary_opt_single_n, all_float, mxz)
337337
#undef REQUIRED_EXTENSIONS
338338

339+
#define REQUIRED_EXTENSIONS streaming_only (AARCH64_FL_SME_F16F16)
340+
DEF_SVE_FUNCTION_GS (svcvt, unary_convertxn, cvt_f32_f16, x2, none)
341+
DEF_SVE_FUNCTION_GS (svcvtl, unary_convertxn, cvt_f32_f16, x2, none)
342+
#undef REQUIRED_EXTENSIONS
343+
339344
#define REQUIRED_EXTENSIONS \
340345
sve_and_sme (AARCH64_FL_SVE2 | AARCH64_FL_SVE_B16B16, \
341346
AARCH64_FL_SME2 | AARCH64_FL_SVE_B16B16)

‎gcc/config/aarch64/aarch64-sve-builtins-sve2.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ namespace aarch64_sve
6161
extern const function_base *const svcdot_lane;
6262
extern const function_base *const svclamp;
6363
extern const function_base *const svcntp;
64+
extern const function_base *const svcvtl;
6465
extern const function_base *const svcvtlt;
6566
extern const function_base *const svcvtn;
6667
extern const function_base *const svcvtx;

‎gcc/config/aarch64/aarch64-sve-builtins.cc‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -296,6 +296,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
296296
#define TYPES_h_bfloat(S, D) \
297297
S (bf16)
298298

299+
/* _f16. */
300+
#define TYPES_h_float(S, D) \
301+
S (f16)
302+
299303
/* _s16
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_u16. */
301305
#define TYPES_h_integer(S, D) \
@@ -450,6 +454,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
450454
#define TYPES_cvt_h_s_float(S, D) \
451455
D (bf16, f32), D (f16, f32)
452456

457+
/* _f32_f16. */
458+
#define TYPES_cvt_f32_f16(S, D) \
459+
D (f32, f16)
460+
453461
/* _f32_f16
454462
_f64_f32. */
455463
#define TYPES_cvt_long(S, D) \
@@ -625,6 +633,10 @@ CONSTEXPR const group_suffix_info group_suffixes[] = {
625633
TYPES_za_bhsd_data (S, D), \
626634
TYPES_reinterpret1 (D, za128)
627635

636+
/* _za16_f16. */
637+
#define TYPES_za_h_float(S, D) \
638+
D (za16, f16)
639+
628640
/* _za32_s8. */
629641
#define TYPES_za_s_b_signed(S, D) \
630642
D (za32, s8)
@@ -744,6 +756,7 @@ DEF_SVE_TYPES_ARRAY (bhs_data);
744756
DEF_SVE_TYPES_ARRAY (bhs_widen);
745757
DEF_SVE_TYPES_ARRAY (c);
746758
DEF_SVE_TYPES_ARRAY (h_bfloat);
759+
DEF_SVE_TYPES_ARRAY (h_float);
747760
DEF_SVE_TYPES_ARRAY (h_integer);
748761
DEF_SVE_TYPES_ARRAY (hs_signed);
749762
DEF_SVE_TYPES_ARRAY (hs_integer);
@@ -772,6 +785,7 @@ DEF_SVE_TYPES_ARRAY (d_data);
772785
DEF_SVE_TYPES_ARRAY (cvt);
773786
DEF_SVE_TYPES_ARRAY (cvt_bfloat);
774787
DEF_SVE_TYPES_ARRAY (cvt_h_s_float);
788+
DEF_SVE_TYPES_ARRAY (cvt_f32_f16);
775789
DEF_SVE_TYPES_ARRAY (cvt_long);
776790
DEF_SVE_TYPES_ARRAY (cvt_narrow_s);
777791
DEF_SVE_TYPES_ARRAY (cvt_narrow);
@@ -793,6 +807,7 @@ DEF_SVE_TYPES_ARRAY (all_za);
793807
DEF_SVE_TYPES_ARRAY (d_za);
794808
DEF_SVE_TYPES_ARRAY (za_bhsd_data);
795809
DEF_SVE_TYPES_ARRAY (za_all_data);
810+
DEF_SVE_TYPES_ARRAY (za_h_float);
796811
DEF_SVE_TYPES_ARRAY (za_s_b_signed);
797812
DEF_SVE_TYPES_ARRAY (za_s_b_unsigned);
798813
DEF_SVE_TYPES_ARRAY (za_s_b_integer);

‎gcc/config/aarch64/aarch64-sve2.md‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,7 @@
9797
;; == Conversions
9898
;; ---- [FP<-FP] Widening conversions
9999
;; ---- [FP<-FP] Narrowing conversions
100+
;; ---- [FP<-FP] Multi-vector widening conversions
100101
;; ---- [FP<-FP] Multi-vector narrowing conversions
101102
;; ---- [FP<-INT] Multi-vector conversions
102103
;; ---- [INT<-FP] Multi-vector conversions
@@ -3116,6 +3117,31 @@
31163117
"fcvtxnt\t%0.<Ventype>, %2/m, %3.<Vetype>"
31173118
)
31183119

3120+
;; -------------------------------------------------------------------------
3121+
;; ---- [FP<-FP] Multi-vector widening conversions
3122+
;; -------------------------------------------------------------------------
3123+
;; Includes the multi-register forms of:
3124+
;; - FCVT
3125+
;; - FCVTL
3126+
;; -------------------------------------------------------------------------
3127+
3128+
(define_insn "extendvnx8hfvnx8sf2"
3129+
[(set (match_operand:VNx8SF 0 "aligned_register_operand" "=Uw2")
3130+
(float_extend:VNx8SF
3131+
(match_operand:VNx8HF 1 "register_operand" "w")))]
3132+
"TARGET_STREAMING_SME_F16F16"
3133+
"fcvt\t%0, %1.h"
3134+
)
3135+
3136+
(define_insn "@aarch64_sve_cvtl<mode>"
3137+
[(set (match_operand:VNx8SF_ONLY 0 "aligned_register_operand" "=Uw2")
3138+
(unspec:VNx8SF_ONLY
3139+
[(match_operand:VNx8HF 1 "register_operand" "w")]
3140+
UNSPEC_FCVTL))]
3141+
"TARGET_STREAMING_SME_F16F16"
3142+
"fcvtl\t%0, %1.h"
3143+
)
3144+
31193145
;; -------------------------------------------------------------------------
31203146
;; ---- [FP<-FP] Multi-vector narrowing conversions
31213147
;; -------------------------------------------------------------------------

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