Add Sipeed SLogic Analyzer Driver Support #275
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sipeed-slogic-analyzer: Add support for SlogicCombo8 feat: use pattern to control active channels feat: capture data and regroup channels feat: now support max 160Msps(2ch) continous and multi channel sipeed-slogic-analyzer: Add support for SlogicBasic16U3 sipeed-slogic-analyzer: feat: use SR_CONF_BUFFERSIZE to configurate the channel sipeed-slogic-analyzer: feat: at least 2 transfers are pending in parallel, and evaluate transfer latency, also fix cancel_transfer must be handled sipeed-slogic-analyzer: feat: attempt to use function pointers to maintain compatibility with Lite 8 sipeed-slogic-analyzer: fix: slogic lite 8 use ep(0x81) sipeed-slogic-analyzer: fix: stop while has no transfers submitted sipeed-slogic-analyzer: fix: skip sending real stop command for slogic lite 8 sipeed-slogic-analyzer: fix: libusb_handle_events at right time, use `%%` and start from 125ms sipeed-slogic-analyzer: fix: transfers not consumed from the end, so just use NUM_MAX_TRANSFERS instead of num_transfers_used sipeed-slogic-analyzer: chore: add udev rules for slogic sipeed-slogic-analyzer: feat: support sample rate and channel configuration sipeed-slogic-analyzer: feat: separate sr_session_send(sdi, &packet) from receive_transfer handler to ensure usb work continuously sipeed-slogic-analyzer: feat: switch back to 5% tolerance and use a continuous count to determine real timeout sipeed-slogic-analyzer: refactor: simplify and reuse data packet format sipeed-slogic-analyzer: perf: use GThread for raw_data_handle to not distrub handle_events sipeed-slogic-analyzer: fix: aux length starts from bit9 and try to split control write in 4 bytes sipeed-slogic-analyzer: feat: add samplerate configuration support sipeed-slogic-analyzer: fix: select updated samplerate base sipeed-slogic-analyzer: fix: use 4MiB size transfers default to clear previously generated EP data sipeed-slogic-analyzer: refactor: consolidate data submission logic by using `slogic_submit_raw_data` Replace multiple data submission implementations with the common `slogic_submit_raw_data` function to maintain consistency and reduce code duplication. sipeed-slogic-analyzer: Prepare for upstream submission * Implement USB streaming thread isolation - Decouples raw data processing from libusb transfers callback - Enables stable 200MHz sampling (16ch) on SlogicBasic16U3 (max bandwidth: up to 430 MiB/s on test) * Windows-specific enhancements - Resolves USB scheduling bottleneck - Support stable 40MHz sampling (8ch) on SlogicCombo8 - Verified on Win10/Win11 platforms (VMs included) Co-authored-by: Shenzhen Sipeed Team <[email protected]> Co-authored-by: taorye <[email protected], [email protected]> sipeed-slogic-analyzer: fix: standardize product name to "SLogic16U3" sipeed-slogic-analyzer: refactor: lift per_transfer_nbytes enumeration into a separate function fix: use libusb_handle_events after to free transfer that submitted in `train_bulk_in_transfer` feat: support to set vref feat: support adjust vref fix: handle libusb_event in a dedicated thread after opening usb device, and set LIBUSB_TRANSFER_FREE_BUFFER. Ensure all transfers can be freed. feat: support test on patten selected tmp: stop sampling after all transfers are freed fix: update samplerates and voltage threshold calculations; handle acquisition abort correctly fix: implement soft trigger logic and manage trigger state in acquisition
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This pull request is the third submission (see previous: #212, #262) for integrating support for the Sipeed SLogic series logic analyzers into libsigrok. The prior two PRs were interrupted before merging; this version has been fully refactored and thoroughly validated. The driver has been thoroughly tested and confirmed to work correctly on Windows, Linux, and macOS platforms! We sincerely invite everyone to pull and test this branch! Your feedback and suggestions are highly appreciated—we are committed to responding actively and working together to further improve this integration. |
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This pull request adds support for the Sipeed SLogic series logic analyzers (SLogic Combo8, SLogic16U3) to libsigrok. Key changes include:
This contribution enables libsigrok to work with Sipeed SLogic logic analyzers, broadening hardware compatibility.