@@ -100,6 +100,8 @@ class Decoder(srd.Decoder):
100100 'values' : (0 , 1 )},
101101 {'id' : 'bitorder' , 'desc' : 'Bit order' ,
102102 'default' : 'msb-first' , 'values' : ('msb-first' , 'lsb-first' )},
103+ {'id' : 'skipbits' , 'desc' : 'Skip bits from start' ,
104+ 'default' : 0 },
103105 {'id' : 'wordsize' , 'desc' : 'Word size' , 'default' : 8 },
104106 )
105107 annotations = (
@@ -131,6 +133,7 @@ def __init__(self):
131133 def reset (self ):
132134 self .samplerate = None
133135 self .bitcount = 0
136+ self .bitsskipped = 0
134137 self .misodata = self .mosidata = 0
135138 self .misobits = []
136139 self .mosibits = []
@@ -200,6 +203,7 @@ def reset_decoder_state(self):
200203 self .misobits = [] if self .have_miso else None
201204 self .mosibits = [] if self .have_mosi else None
202205 self .bitcount = 0
206+ self .bitsskipped = 0
203207
204208 def cs_asserted (self , cs ):
205209 active_low = (self .options ['cs_polarity' ] == 'active-low' )
@@ -310,6 +314,10 @@ def find_clk_edge(self, miso, mosi, clk, cs, first):
310314 elif mode == 3 and clk == 0 : # Sample on rising clock edge
311315 return
312316
317+ if self .bitsskipped < self .options ["skipbits" ]:
318+ self .bitsskipped += 1
319+ return
320+
313321 # Found the correct clock edge, now get the SPI bit(s).
314322 self .handle_bit (miso , mosi , clk , cs )
315323
0 commit comments