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kywwilson11xiaoxiang781216
kywwilson11
authored and
xiaoxiang781216
committed
Initial commit for STM32G0 dma support. Added DMA mux mappings. Added Kconfig for enabling DMA2. Added basic defines for number of channels and mux channels in dma_v1mux.
Added subclasses of STM32G0 (such as STM32G07X) to Kconfig for use in dmamux driver. Added definitions to stm32g0_dmamux.h. Added configuration of number of dma and dmamux channels. Added missing dma mappings for stm32g0. Remove reserved defines. Formatting fixes. Added DMA2 IRQ mappings for STM32G0B and STM32G0C. Changed STM32_DMAMUX_BASE to STM32_DMAMUX1_BASE to align with stm32_dma_v1mux.c and C0 defines. Provide correct mapping for ADC1_DMA_CHAN. Add STM32F0L0G0_HAVE_ADC1_DMA to STM32G0. Add support for continuous mode to the ADC. Also added support to set smp1 and smp2 in board.h, as well as smpsel. Removed unnecessary selects of STM32F0L0G0_STM32G0. Changed board level files to properly define A0-A3 on nucleo-g0b1re. Add new Kconfig changes. Made combined configs for STM32G0. Ex. STM32G0BX for STM32G0B0 and STM32G0B1. Fixed defines and references in Kconfig and stm32_dma_v1mux.c Defined adc_sampletime_write and adc_sampletime_set. Changed adc_sample_time_s structure to be much simpler. Old way made no sense. You can only have 2 sample times, so defining one for each channel makes no sense. The new adc_sample_time_s contains smp1, smp2, and smpsel. Also define ADC_HAVE_SMPR_SMP2 for STM32C0. Added adc_sampletime_write and adc_sampletime_set. Altered adc_sample_time_s structure to be more appropriate for g0 and c0. Only two sample times can be defined. Added rcc support for DMA2. Added defconfig for nucleo-g0b1re:adc_dma config. Restore correct Kconfig from my original branch Removed redundant ifdefs. If we select for G0 and C0, we know they have SMP2. Fixed formatting. Formatting feedback. Aligned columns in irq and dma headers.
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13 files changed

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13 files changed

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‎arch/arm/include/stm32f0l0g0/stm32g0_irq.h‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,16 @@
7979
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH6 */
8080
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_EXTINT + 11) /* 11: DMA1_CH7 */
8181
#define STM32_IRQ_DMAMUX (STM32_IRQ_EXTINT + 11) /* 11: DMAMUX */
82+
83+
#if defined(CONFIG_STM32F0L0G0_STM32G0BX) || \
84+
defined(CONFIG_STM32F0L0G0_STM32G0C1)
85+
# define STM32_IRQ_DMA2CH1 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH1 */
86+
# define STM32_IRQ_DMA2CH2 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH2 */
87+
# define STM32_IRQ_DMA2CH3 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH3 */
88+
# define STM32_IRQ_DMA2CH4 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH4 */
89+
# define STM32_IRQ_DMA2CH5 (STM32_IRQ_EXTINT + 11) /* 11: DMA2_CH5 */
90+
#endif
91+
8292
#define STM32_IRQ_ADC (STM32_IRQ_EXTINT + 12) /* 12: ADC */
8393
#define STM32_IRQ_EXTI17_18 (STM32_IRQ_EXTINT + 12) /* 12: EXTI_17_18 */
8494

‎arch/arm/src/stm32f0l0g0/Kconfig‎

Lines changed: 47 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1267,13 +1267,19 @@ config STM32F0L0G0_STM32G030
12671267
bool
12681268
default n
12691269
select STM32F0L0G0_STM32G0
1270+
select STM32F0L0G0_STM32G03X
12701271

12711272
config STM32F0L0G0_STM32G031
12721273
bool
12731274
default n
12741275
select STM32F0L0G0_STM32G0
1276+
select STM32F0L0G0_STM32G03X
12751277
select STM32F0L0G0_HAVE_LPUART1
12761278

1279+
config STM32F0L0G0_STM32G03X
1280+
bool
1281+
default n
1282+
12771283
config STM32F0L0G0_STM32G041
12781284
bool
12791285
default n
@@ -1286,21 +1292,25 @@ config STM32F0L0G0_STM32G050
12861292
bool
12871293
default n
12881294
select STM32F0L0G0_STM32G0
1289-
select STM32F0L0G0_HAVE_TIM6
1290-
select STM32F0L0G0_HAVE_TIM7
1295+
select STM32F0L0G0_STM32G05X
12911296

12921297
config STM32F0L0G0_STM32G051
12931298
bool
12941299
default n
12951300
select STM32F0L0G0_STM32G0
1301+
select STM32F0L0G0_STM32G05X
12961302
select STM32F0L0G0_HAVE_DAC1
12971303
select STM32F0L0G0_HAVE_COMP1
12981304
select STM32F0L0G0_HAVE_COMP2
1299-
select STM32F0L0G0_HAVE_TIM6
1300-
select STM32F0L0G0_HAVE_TIM7
13011305
select STM32F0L0G0_HAVE_TIM15
13021306
select STM32F0L0G0_HAVE_LPUART1
13031307

1308+
config STM32F0L0G0_STM32G05X
1309+
bool
1310+
default n
1311+
select STM32F0L0G0_HAVE_TIM6
1312+
select STM32F0L0G0_HAVE_TIM7
1313+
13041314
config STM32F0L0G0_STM32G061
13051315
bool
13061316
default n
@@ -1319,30 +1329,29 @@ config STM32F0L0G0_STM32G070
13191329
bool
13201330
default n
13211331
select STM32F0L0G0_STM32G0
1322-
select STM32F0L0G0_HAVE_USART3
1323-
select STM32F0L0G0_HAVE_USART4
1324-
select STM32F0L0G0_HAVE_TIM6
1325-
select STM32F0L0G0_HAVE_TIM7
1326-
select STM32F0L0G0_HAVE_TIM15
1327-
select STM32F0L0G0_HAVE_UCPD1
1328-
select STM32F0L0G0_HAVE_UCPD2
1332+
select STM32F0L0G0_STM32G07X
13291333

13301334
config STM32F0L0G0_STM32G071
13311335
bool
13321336
default n
13331337
select STM32F0L0G0_STM32G0
1334-
select STM32F0L0G0_HAVE_USART3
1335-
select STM32F0L0G0_HAVE_USART4
1338+
select STM32F0L0G0_STM32G07X
13361339
select STM32F0L0G0_HAVE_DAC1
13371340
select STM32F0L0G0_HAVE_COMP1
13381341
select STM32F0L0G0_HAVE_COMP2
1342+
select STM32F0L0G0_HAVE_CEC
1343+
select STM32F0L0G0_HAVE_LPUART1
1344+
1345+
config STM32F0L0G0_STM32G07X
1346+
bool
1347+
default n
1348+
select STM32F0L0G0_HAVE_USART3
1349+
select STM32F0L0G0_HAVE_USART4
13391350
select STM32F0L0G0_HAVE_TIM6
13401351
select STM32F0L0G0_HAVE_TIM7
13411352
select STM32F0L0G0_HAVE_TIM15
13421353
select STM32F0L0G0_HAVE_UCPD1
13431354
select STM32F0L0G0_HAVE_UCPD2
1344-
select STM32F0L0G0_HAVE_CEC
1345-
select STM32F0L0G0_HAVE_LPUART1
13461355

13471356
config STM32F0L0G0_STM32G081
13481357
bool
@@ -1367,30 +1376,24 @@ config STM32F0L0G0_STM32G0B0
13671376
bool
13681377
default n
13691378
select STM32F0L0G0_STM32G0
1370-
select STM32F0L0G0_HAVE_DMA2
1371-
select STM32F0L0G0_HAVE_USART3
1372-
select STM32F0L0G0_HAVE_USART4
1373-
select STM32F0L0G0_HAVE_USART5
1374-
select STM32F0L0G0_HAVE_USART6
1375-
select STM32F0L0G0_HAVE_LPUART1
1376-
select STM32F0L0G0_HAVE_LPUART2
1377-
select STM32F0L0G0_HAVE_CRS
1378-
select STM32F0L0G0_HAVE_TIM4
1379-
select STM32F0L0G0_HAVE_TIM6
1380-
select STM32F0L0G0_HAVE_TIM7
1381-
select STM32F0L0G0_HAVE_TIM15
1382-
select STM32F0L0G0_HAVE_I2C3
1383-
select STM32F0L0G0_HAVE_SPI3
1384-
select STM32F0L0G0_HAVE_I2S2
1385-
select STM32F0L0G0_HAVE_USBDEV
1386-
select STM32F0L0G0_HAVE_UCPD1
1387-
select STM32F0L0G0_HAVE_UCPD2
1388-
select STM32F0L0G0_HAVE_HSI48
1379+
select STM32F0L0G0_STM32G0BX
13891380

13901381
config STM32F0L0G0_STM32G0B1
13911382
bool
13921383
default n
13931384
select STM32F0L0G0_STM32G0
1385+
select STM32F0L0G0_STM32G0BX
1386+
select STM32F0L0G0_HAVE_DAC1
1387+
select STM32F0L0G0_HAVE_COMP1
1388+
select STM32F0L0G0_HAVE_COMP2
1389+
select STM32F0L0G0_HAVE_COMP3
1390+
select STM32F0L0G0_HAVE_FDCAN1
1391+
select STM32F0L0G0_HAVE_FDCAN2
1392+
select STM32F0L0G0_HAVE_CEC
1393+
1394+
config STM32F0L0G0_STM32G0BX
1395+
bool
1396+
default n
13941397
select STM32F0L0G0_HAVE_DMA2
13951398
select STM32F0L0G0_HAVE_USART3
13961399
select STM32F0L0G0_HAVE_USART4
@@ -1399,10 +1402,6 @@ config STM32F0L0G0_STM32G0B1
13991402
select STM32F0L0G0_HAVE_LPUART1
14001403
select STM32F0L0G0_HAVE_LPUART2
14011404
select STM32F0L0G0_HAVE_CRS
1402-
select STM32F0L0G0_HAVE_DAC1
1403-
select STM32F0L0G0_HAVE_COMP1
1404-
select STM32F0L0G0_HAVE_COMP2
1405-
select STM32F0L0G0_HAVE_COMP3
14061405
select STM32F0L0G0_HAVE_TIM4
14071406
select STM32F0L0G0_HAVE_TIM6
14081407
select STM32F0L0G0_HAVE_TIM7
@@ -1413,9 +1412,6 @@ config STM32F0L0G0_STM32G0B1
14131412
select STM32F0L0G0_HAVE_USBDEV
14141413
select STM32F0L0G0_HAVE_UCPD1
14151414
select STM32F0L0G0_HAVE_UCPD2
1416-
select STM32F0L0G0_HAVE_FDCAN1
1417-
select STM32F0L0G0_HAVE_FDCAN2
1418-
select STM32F0L0G0_HAVE_CEC
14191415
select STM32F0L0G0_HAVE_HSI48
14201416

14211417
config STM32F0L0G0_STM32G0C1
@@ -3698,6 +3694,16 @@ config STM32F0L0G0_ADC1_EXTSEL
36983694
---help---
36993695
Enable EXTSEL for ADC1.
37003696

3697+
config STM32F0L0G0_ADC1_CONTINUOUS
3698+
bool "Enable ADC1 Continuous Conversion Mode"
3699+
default n
3700+
depends on STM32F0L0G0_ADC1
3701+
---help---
3702+
If enabled, the ADC will operate in continuous conversion mode.
3703+
Otherwise, it will perform single conversions.
3704+
Note: Continuous and discontinuous mode cannot be defined at
3705+
the same time
3706+
37013707
endmenu # ADC Configuration
37023708

37033709
menu "SPI Configuration"

‎arch/arm/src/stm32f0l0g0/hardware/stm32_adc.h‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -243,8 +243,9 @@
243243
#define ADC_SMPR_SMP2_SHIFT (4) /* Bits 4-6: Sampling time selection 2 */
244244
#define ADC_SMPR_SMP2_MASK (7 << ADC_SMPR_SMP_SHIFT)
245245
#define ADC_SMPR_SMPSEL_SHIFT (8) /* Bits 8-26: channel-x sampling time selection */
246-
#if defined(CONFIG_ARCH_CHIP_STM32G0)
247-
# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..18] and smp = 1 or 0 */
246+
#if defined(CONFIG_ARCH_CHIP_STM32G0) || defined(CONFIG_ARCH_CHIP_STM32C0)
247+
# define ADC_SMPR_SMPSEL(ch, smp) ((smp) << (ADC_SMPR_SMPSEL_SHIFT + ch)) /* ch = [0..22] and smp = 0 or 1 */
248+
# define ADC_SMPSEL(ch, smp) ((smp) << (ch)) /* For use in adc_sampletime_set */
248249
#else
249250
# define ADC_SMPR_SMPSEL(ch, smp) (smp << ADC_SMPR_SMPSEL_SHIFT)
250251
#endif

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