|
| 1 | +=============== |
| 2 | +Seqcount |
| 3 | +=============== |
| 4 | + |
| 5 | +Summary |
| 6 | +======= |
| 7 | + |
| 8 | +This an efficient ``Seqlock`` (sequential lock) mechanism suitable for |
| 9 | +concurrent scenarios with frequent reads and rare writes. |
| 10 | +``Seqlock`` enables lock-free reading while ensuring data consistency |
| 11 | +through sequence counting. |
| 12 | + |
| 13 | +Core Features |
| 14 | +------------- |
| 15 | + |
| 16 | +1. Lock-Free Reading |
| 17 | +~~~~~~~~~~~~~~~~~~~~ |
| 18 | + |
| 19 | +- Readers access shared data without acquiring locks, eliminating lock |
| 20 | + contention |
| 21 | +- Sequence number tracking detects data modifications during read operations |
| 22 | +- Retry mechanism guarantees read consistency |
| 23 | + |
| 24 | +2. Write Protection |
| 25 | +~~~~~~~~~~~~~~~~~~~ |
| 26 | + |
| 27 | +- Writers utilize atomic operations and interrupt protection for exclusive |
| 28 | + access |
| 29 | +- Sequence number parity indicates write state (even: readable, odd: writing) |
| 30 | +- SMP environments employ memory barriers for operation ordering |
| 31 | + |
| 32 | +Main Interfaces |
| 33 | +--------------- |
| 34 | + |
| 35 | +Initialization |
| 36 | +~~~~~~~~~~~~~~ |
| 37 | + |
| 38 | +.. code-block:: c |
| 39 | +
|
| 40 | + void seqlock_init(seqcount_t *s); |
| 41 | +
|
| 42 | +Read Operations |
| 43 | +~~~~~~~~~~~~~~~ |
| 44 | + |
| 45 | +.. code-block:: c |
| 46 | +
|
| 47 | + uint32_t read_seqbegin(const seqcount_t *s); |
| 48 | + uint32_t read_seqretry(const seqcount_t *s, uint32_t start); |
| 49 | +
|
| 50 | +Reader usage pattern: |
| 51 | + |
| 52 | +.. code-block:: c |
| 53 | +
|
| 54 | + uint32_t seq; |
| 55 | + do { |
| 56 | + seq = read_seqbegin(&seqlock); |
| 57 | + // Read shared data |
| 58 | + } while (read_seqretry(&seqlock, seq)); |
| 59 | +
|
| 60 | +Write Operations |
| 61 | +~~~~~~~~~~~~~~~~ |
| 62 | + |
| 63 | +.. code-block:: c |
| 64 | +
|
| 65 | + irqstate_t write_seqlock_irqsave(seqcount_t *s); |
| 66 | + void write_sequnlock_irqrestore(seqcount_t *s, irqstate_t flags); |
| 67 | +
|
| 68 | +Writer usage pattern: |
| 69 | + |
| 70 | +.. code-block:: c |
| 71 | +
|
| 72 | + irqstate_t flags = write_seqlock_irqsave(&seqlock); |
| 73 | + // Modify shared data |
| 74 | + write_sequnlock_irqrestore(&seqlock, flags); |
| 75 | +
|
| 76 | +Technical Details |
| 77 | +----------------- |
| 78 | + |
| 79 | +1. Sequence Number Mechanism |
| 80 | +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 81 | + |
| 82 | +- Sequence counter initializes to 0 (even) |
| 83 | +- Write start increments by 1 (becomes odd) |
| 84 | +- Write completion increments by 1 (returns to even) |
| 85 | + |
| 86 | +2. Memory Barriers |
| 87 | +~~~~~~~~~~~~~~~~~~ |
| 88 | + |
| 89 | +- SMP systems utilize appropriate read/write memory barriers |
| 90 | +- ``SMP_WMB()``: Write memory barrier |
| 91 | +- ``SMP_RMB()``: Read memory barrier |
| 92 | +- Ensures operation ordering and memory visibility |
| 93 | + |
| 94 | +3. Atomic Operations |
| 95 | +~~~~~~~~~~~~~~~~~~~~ |
| 96 | + |
| 97 | +- SMP environments employ atomic read/write and CAS operations |
| 98 | +- Prevents data races and maintains consistency |
| 99 | + |
| 100 | +4. Interrupt Protection |
| 101 | +~~~~~~~~~~~~~~~~~~~~~~~ |
| 102 | + |
| 103 | +- Write operations disable interrupts |
| 104 | +- Prevents interrupt handlers from interfering with critical sections |
| 105 | + |
| 106 | +Applicable Scenarios |
| 107 | +-------------------- |
| 108 | + |
| 109 | +- Read operations significantly outnumber write operations |
| 110 | +- Readers can tolerate temporary data inconsistency |
| 111 | +- High-performance read operations are required |
| 112 | + |
| 113 | +Performance Advantages |
| 114 | +---------------------- |
| 115 | + |
| 116 | +- Read operations completely lock-free with minimal overhead |
| 117 | +- Significant performance improvement for read-intensive applications |
| 118 | + |
| 119 | +This implementation accounts for differences between SMP and uniprocessor |
| 120 | +environments, ensuring correct operation across various configurations. |
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