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kywwilson11xiaoxiang781216
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arch/arm/stm32h5: Initial Driver for STM32H5 Digital Temperature Sensor (DTS)
- Committing initial code for DTS. Missing ISR. Works for PCLK1. Cannot get to work for LSE. - Pushing everything. Working with LSE now. - Many fixes. Fixed interrupt setting. Added data structures. - Changed interrupt handling. Removed FARs. Added Kconfig options for selecting interrupts. - Updated info and formatting. - Formatting fixes. - Formatting. - Changed iten to regval. - Removed Triggger - Formatting fixes per Pull request. - Changed private_types to have stm32_ prefix. Used depends on for DTS Kconfig Menu. Fixed formatting per PR. - Fixed spacing of function prototypes. - Fixed indent on line - Added documentation for STM32H5 and Nucleo-H563ZI regarding DTS. Also added GPDMA support to STM32H5 documentation (previous PR). Made stm32_dts.c more modular. stm32_dts_activate is now much more readable. Added comments/descriptions to private functions. Lastly, added a nucleo-h563zi:dts configuration.
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‎Documentation/platforms/arm/stm32h5/boards/nucleo-h563zi/index.rst‎

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@@ -145,6 +145,13 @@ usbnsh:
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This configuration provides a basic NuttShell through the USB User interface.
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dts:
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--------
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This configuration configures the digital temperature sensor (DTS)
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at /dev/uorb/sensor_temp0 and provides the test application
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sensortest. E.g. sensortest -n 10 temp0
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References
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===========
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‎Documentation/platforms/arm/stm32h5/index.rst‎

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@@ -35,8 +35,10 @@ Peripheral Support Notes
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========== ======= =====
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ADC Yes
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ETH Yes
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DTS Yes Software trigger only.
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FLASH Yes Hardware defines only.
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FDCAN Yes
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GPDMA Yes
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GPIO Yes
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I2C Yes
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ICACHE Yes
@@ -59,11 +61,9 @@ DBG No
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DCACHE No
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DCMI No
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DLYB No
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DTS No
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EXTI No
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FMAC No
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FSMC No
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GPDMA No
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GTZC No
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HASH No
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I3C No

‎arch/arm/src/stm32h5/Kconfig‎

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@@ -359,6 +359,14 @@ config STM32H5_DMA2
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select STM32H5_DMA
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select ARCH_DMA
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config STM32H5_DTS
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bool "DTS"
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default n
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---help---
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Enable support for the on‑die digital temperature sensor (DTS)
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built into STM32H5 devices. When enabled, the driver will register
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a `/dev/sensor_tempX` device using the common NuttX sensor framework.
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config STM32H5_ETHMAC
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bool "Ethernet MAC"
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default n
@@ -625,6 +633,107 @@ config STM32H5_USBFS
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endmenu # STM32H5 Peripheral Selection
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menu "DTS Configuration"
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depends on STM32H5_DTS
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config STM32H5_DTS_REFCLK_LSE
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bool "Use LSE (32.768 kHz crystal) as DTS reference clock"
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default n
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---help---
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Select the low‑speed external (LSE) oscillator as the reference clock
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for the DTS. When enabled, DTS_CFGR1.REFCLK_SEL=1 and the driver will
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measure FM(T) pulses over N LSE cycles.
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If disabled, the DTS will use the APB‑bus clock (PCLK) as the reference
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(REFCLK_SEL=0) and you must supply a valid HSREF_CLK_DIV to keep the
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calibration prescaler ≤ 1 MHz.
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config STM32H5_DTS_SMP_TIME
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int "DTS sampling time (TS1_SMP_TIME[3:0])"
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default 1
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range 1 15
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---help---
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Number of reference‑clock cycles (PCLK or LSE) counted per
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DTS measurement. Valid range 1 (1 cycle) through 15 (15 cycles).
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config STM32H5_DTS_TRIGGER
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int "DTS hardware trigger source (TS1_INTRIG_SEL[3:0])"
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default 0
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---help---
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If non‑zero, DTS will start measurements on the rising edge of
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the selected hardware line. Values match RM0481 Table 275:
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0=Software Trigger, 1=LPTIM1_CH1, 
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2=LPTIM2_CH1, 3=LPTIM3_CH1, 4=EXTI13, 5-15 are reserved.
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config STM32H5_DTS_LOW_THRESHOLD
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int "DTS low‑threshold (°C)"
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default 0
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---help---
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The temperature (in whole °C) below which the DTS window comparator will
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assert the low‑threshold flag (TS1_ITLF). To disable, set equal to 0.
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config STM32H5_DTS_HIGH_THRESHOLD
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int "DTS high‑threshold (°C)"
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default 100
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---help---
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The temperature (in whole °C) above which the DTS window comparator will
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assert the high‑threshold flag (TS1_ITHF). Must be >= LOW_THRESHOLD.
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config STM32H5_DTS_ITEN_ITEF
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bool "Enable DTS end‑of‑measurement interrupt (TS1_ITEF)"
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default y
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---help---
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Enable the synchronous “end of measurement” interrupt for the
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digital temperature sensor. When set, the driver will attach
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and unmask TS1_ITEF and will call your ISR on every fresh sample.
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config STM32H5_DTS_ITEN_ITLF
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bool "Enable DTS low‑threshold interrupt (TS1_ITLF)"
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default n
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---help---
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Enable the synchronous “low threshold crossed” interrupt for the
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digital temperature sensor. When set, the driver will unmask
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TS1_ITLF so you can get notified whenever the measured value
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drops below your programmed low‑threshold.
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config STM32H5_DTS_ITEN_ITHF
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bool "Enable DTS high‑threshold interrupt (TS1_ITHF)"
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default n
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---help---
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Enable the synchronous “high threshold crossed” interrupt for the
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digital temperature sensor. When set, the driver will unmask
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TS1_ITHF so you can get notified whenever the measured value
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exceeds your programmed high‑threshold.
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config STM32H5_DTS_AITEN_AITEF
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bool "Enable DTS asynchronous end‑of‑measurement interrupt (TS1_AITEF)"
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depends on STM32H5_DTS_REFCLK_LSE
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default n
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---help---
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Enable the asynchronous end‑of‑measurement interrupt. This will
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set TS1_AITEEN in DTS_ITENR and cause an _asynchronous_ wakeup
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event when a conversion completes (in Stop/Sleep modes).
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config STM32H5_DTS_AITEN_AITLF
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bool "Enable DTS asynchronous low‑threshold interrupt (TS1_AITLF)"
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depends on STM32H5_DTS_REFCLK_LSE
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default n
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---help---
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Enable the asynchronous low‑threshold comparator interrupt. This
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will set TS1_AITLEN in DTS_ITENR and generate a wakeup event
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when the measurement drops below your low threshold.
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config STM32H5_DTS_AITEN_AITHF
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bool "Enable DTS asynchronous high‑threshold interrupt (TS1_AITHF)"
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depends on STM32H5_DTS_REFCLK_LSE
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default n
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---help---
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Enable the asynchronous high‑threshold comparator interrupt. This
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will set TS1_AITHEN in DTS_ITENR and generate a wakeup event
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when the measurement exceeds your high threshold.
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endmenu # DTS Configuration
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config STM32H5_FLASH_PREFETCH
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bool "Enable FLASH Pre-fetch"
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default y

‎arch/arm/src/stm32h5/Make.defs‎

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@@ -92,6 +92,10 @@ ifeq ($(CONFIG_STM32H5_DMA),y)
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CHIP_CSRCS += stm32_dma.c
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endif
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ifeq ($(CONFIG_STM32H5_DTS),y)
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CHIP_CSRCS += stm32_dts.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)

‎arch/arm/src/stm32h5/hardware/stm32_dts.h‎

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@@ -71,6 +71,8 @@
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# define DTS_CFGR1_TS1_INTRIG_SEL_LPTIM2_CH1 (0x2 << DTS_CFGR1_TS1_INTRIG_SEL_SHIFT)
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# define DTS_CFGR1_TS1_INTRIG_SEL_LPTIM3_CH1 (0x3 << DTS_CFGR1_TS1_INTRIG_SEL_SHIFT)
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# define DTS_CFGR1_TS1_INTRIG_SEL_EXTI13 (0x4 << DTS_CFGR1_TS1_INTRIG_SEL_SHIFT)
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#define DTS_CFGR1_TS1_INTRIG(n) \
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(((n) << DTS_CFGR1_TS1_INTRIG_SEL_SHIFT) & DTS_CFGR1_TS1_INTRIG_SEL_MASK)
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#define DTS_CFGR1_TS1_SMP_TIME_SHIFT (16) /* Bits 16-19: Sampling time */
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#define DTS_CFGR1_TS1_SMP_TIME_MASK (0xf << DTS_CFGR1_TS1_SMP_TIME_SHIFT)
@@ -86,26 +88,26 @@
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/* Temperature sensor T0 value register 1 */
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#define DTS_T0VALR1_TS1_FMT0_SHIFT (0) /* Engineering value for frequency at T0 */
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#define DTS_T0VALR1_TS1_FMT0_MASK (0xff << DTS_T0VALR1_TS1_FMT0_SHIFT)
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#define DTS_T0VALR1_TS1_FMT0_MASK (0xffff << DTS_T0VALR1_TS1_FMT0_SHIFT)
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#define DTS_T0VALR1_TS1_T0_SHIFT (16) /* Engineering value of T0 */
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#define DTS_T0VALR1_TS1_T0_MASK (0b11 << DTS_T0VALR1_TS1_T0_SHIFT)
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/* Temperature sensor ramp value register */
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#define DTS_RAMPVALR_TS1_RAMP_COEFF_SHIFT (0) /* Engineering value of ramp coefficient */
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#define DTS_RAMPVALR_TS1_RAMP_COEFF_MASK (0xff << DTS_RAMPVALR_TS1_RAMP_COEFF_SHIFT)
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#define DTS_RAMPVALR_TS1_RAMP_COEFF_MASK (0xffff << DTS_RAMPVALR_TS1_RAMP_COEFF_SHIFT)
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/* Temperature sensor interrupt threshold register 1 */
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#define DTS_ITR1_TS1_LITTHD_SHIFT (0) /* High interrupt threshold */
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#define DTS_ITR1_TS1_LITTHD_MASK (0xff << DTS_ITR1_TS1_LITTHD_SHIFT)
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#define DTS_ITR1_TS1_LITTHD_MASK (0xffff << DTS_ITR1_TS1_LITTHD_SHIFT)
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#define DTS_ITR1_TS1_HITTHD_SHIFT (16) /* Low interrupt threshold */
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#define DTS_ITR1_TS1_HITTHD_MASK (0xff << DTS_ITR1_TS1_HITTHD_SHIFT)
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#define DTS_ITR1_TS1_HITTHD_MASK (0xffff << DTS_ITR1_TS1_HITTHD_SHIFT)
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/* Temperature sensor data register */
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#define DTS_DR_TS1_MFREQ_SHIFT (0)
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#define DTS_DR_TS1_MFREQ_MASK (0xff << DTS_DR_TS1_MFREQ_SHIFT)
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#define DTS_DR_TS1_MFREQ_MASK (0xffff << DTS_DR_TS1_MFREQ_SHIFT)
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/* Temperature sensor status register */
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@@ -134,6 +136,7 @@
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#define DTS_ICIFR_CAITEF (1 << 4) /* Asynchronous interrupt clear flag: end of measurement */
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#define DTS_ICIFR_CAITLF (1 << 5) /* Asynchronous interrupt clear flag: low threshold */
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#define DTS_ICIFR_CAITHF (1 << 6) /* Asynchronous interrupt clear flag: high threshold */
139+
#define DTS_ICIFR_ALL (0x77) /* All interrupts */
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/* Temperature sensor option register */
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‎arch/arm/src/stm32h5/hardware/stm32h5xxx_rcc.h‎

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@@ -264,13 +264,13 @@
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# define RCC_CFGR2_HPRE_SYSCLKd256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
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# define RCC_CFGR2_HPRE_SYSCLKd512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
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#define RCC_CFGR2_PPRE1_SHIFT (0) /* Bits 6-4: PPRE1 Prescaler */
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#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 6-4: PPRE1 Prescaler */
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#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_PPRE1_SHIFT)
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# define RCC_CFGR2_PPRE1_HCLK1 (0 << RCC_CFGR2_PPRE1_SHIFT) /* 0xx: HCLK1 not divided */
270-
# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 1000: HCLK1 divided by 2 */
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# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 1001: HCLK1 divided by 4 */
272-
# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 1010: HCLK1 divided by 8 */
273-
# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 1011: HCLK1 divided by 16 */
270+
# define RCC_CFGR2_PPRE1_HCLK1d2 (4 << RCC_CFGR2_PPRE1_SHIFT) /* 100: HCLK1 divided by 2 */
271+
# define RCC_CFGR2_PPRE1_HCLK1d4 (5 << RCC_CFGR2_PPRE1_SHIFT) /* 101: HCLK1 divided by 4 */
272+
# define RCC_CFGR2_PPRE1_HCLK1d8 (6 << RCC_CFGR2_PPRE1_SHIFT) /* 110: HCLK1 divided by 8 */
273+
# define RCC_CFGR2_PPRE1_HCLK1d16 (7 << RCC_CFGR2_PPRE1_SHIFT) /* 111: HCLK1 divided by 16 */
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275275
#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 10-8: PPRE2 Prescaler */
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#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT)

‎arch/arm/src/stm32h5/stm32.h‎

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@@ -39,6 +39,7 @@
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#include "chip.h"
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#include "stm32_adc.h"
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#include "stm32_dbgmcu.h"
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#include "stm32_dts.h"
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#include "stm32_flash.h"
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#include "stm32_gpio.h"
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#include "stm32_i2c.h"

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