|
| 1 | +from session import Session |
| 2 | +from assembler import Assembler |
| 3 | +from commands import * |
| 4 | + |
| 5 | +class CompilerSession(Session): |
| 6 | + |
| 7 | + def __init__(self, pos, writer, namespace, page_size=64, **kwargs): |
| 8 | + self.page_size = page_size |
| 9 | + super(CompilerSession, self).__init__(pos, writer, namespace, **kwargs) |
| 10 | + self.scope.variables.update({ |
| 11 | + 'memory_address': 'ma', |
| 12 | + 'memory_buffer': 'mb', |
| 13 | + 'memory_slot': ('ms_%d', range(self.page_size)) |
| 14 | + }) |
| 15 | + self.add_page() |
| 16 | + |
| 17 | + def add_page(self): |
| 18 | + setter = Subsequence() |
| 19 | + getter = Subsequence() |
| 20 | + dump = ["["] |
| 21 | + |
| 22 | + mbr = Var('memory_buffer') |
| 23 | + mar = Var('memory_address') |
| 24 | + |
| 25 | + for i in range(self.page_size): |
| 26 | + slot = Var('memory_slot', i) |
| 27 | + dump.append(slot) |
| 28 | + if i != self.page_size - 1: |
| 29 | + dump.append(",") |
| 30 | + |
| 31 | + setter.add_command(OpAssign(slot, mbr).where(SelEquals(mar, i))) |
| 32 | + getter.add_command(OpAssign(mbr, slot).where(SelEquals(mar, i))) |
| 33 | + |
| 34 | + self.scope.add_function_names(('mem_set', 'mem_get', 'mem_dump')) |
| 35 | + self.add_subsequence('mem_set', setter) |
| 36 | + self.add_subsequence('mem_get', getter) |
| 37 | + s = Subsequence() |
| 38 | + dump.append("]") |
| 39 | + s.add_command(Tellraw(dump, 'a')) |
| 40 | + self.add_subsequence('mem_dump', s) |
| 41 | + |
| 42 | + def extended_setup(self, up, down): |
| 43 | + # temp |
| 44 | + up.append(SetConst(Var('stack_pointer'), 0).resolve(self.scope)) |
| 45 | + for i in range(self.page_size): |
| 46 | + slot = Var('memory_slot', i) |
| 47 | + up.append(SetConst(slot, 0).resolve(self.scope)) |
| 48 | + |
| 49 | +class ExtendedAssembler(Assembler): |
| 50 | + |
| 51 | + def __init__(self): |
| 52 | + super(ExtendedAssembler, self).__init__() |
| 53 | + self.instructions.update({ |
| 54 | + 'MOVIND': self.handle_mov_ind, |
| 55 | + 'MOVINDD': self.handle_mov_ind_d, |
| 56 | + 'MOVINDS': self.handle_mov_ind_s |
| 57 | + }) |
| 58 | + |
| 59 | + def handle_mov_ind(self, src, s_off, dest, d_off): |
| 60 | + """Move indirect src to indirect dest""" |
| 61 | + src, dest = self.get_src_dest(src, dest) |
| 62 | + s_off = self.resolve_ref(*s_off) |
| 63 | + d_off = self.resolve_ref(*d_off) |
| 64 | + assert type(s_off) == int |
| 65 | + assert type(d_off) == int |
| 66 | + self.add_command(OpAssign(Var('memory_address'), src)) |
| 67 | + if s_off != 0: |
| 68 | + self.add_command(AddConst(Var('memory_address'), s_off)) |
| 69 | + self.add_command(Function('mem_get')) |
| 70 | + self.add_command(OpAssign(Var('memory_address'), dest)) |
| 71 | + if d_off != 0: |
| 72 | + self.add_command(AddConst(Var('memory_address'), d_off)) |
| 73 | + self.add_command(Function('mem_set')) |
| 74 | + |
| 75 | + def handle_mov_ind_d(self, src, dest, d_off): |
| 76 | + """Move src to indirect dest""" |
| 77 | + src, dest = self.get_src_dest(src, dest) |
| 78 | + offset = self.resolve_ref(*d_off) |
| 79 | + assert type(offset) == int |
| 80 | + self.add_command(self.assign_op(Var('memory_buffer'), src)) |
| 81 | + self.add_command(OpAssign(Var('memory_address'), dest)) |
| 82 | + if offset != 0: |
| 83 | + self.add_command(AddConst(Var('memory_address'), offset)) |
| 84 | + self.add_command(Function('mem_set')) |
| 85 | + |
| 86 | + def handle_mov_ind_s(self, src, s_off, dest): |
| 87 | + """Move indirect src to dest""" |
| 88 | + src, dest = self.get_src_dest(src, dest) |
| 89 | + offset = self.resolve_ref(*s_off) |
| 90 | + assert type(offset) == int |
| 91 | + self.add_command(self.assign_op(Var('memory_address'), src)) |
| 92 | + if offset != 0: |
| 93 | + self.add_command(AddConst(Var('memory_address'), offset)) |
| 94 | + self.add_command(Function('mem_get')) |
| 95 | + self.add_command(OpAssign(dest, Var('memory_buffer'))) |
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