qwe

Author: simonsterer061

info.yaml

@@ -17,7 +17,7 @@ project:
   # Source files must be in ./src and you must list each source file separately, one per line.
   # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
-    - "test.vs"
+    - "tt_um_test.vs"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).

src/test.vs src/tt_um_test.vssrc/test.vs renamed to src/tt_um_test.vs

@@ -6,7 +6,7 @@ SIM ?= icarus
 FST ?= -fst # Use more efficient FST format
 TOPLEVEL_LANG ?= SystemVerilog
 SRC_DIR = $(PWD)/../src
-PROJECT_SOURCES = test.vs
+PROJECT_SOURCES = tett_um_test.vs
 
 ifneq ($(GATES),yes)