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dpaoliellosivadeilra
dpaoliello
authored and
sivadeilra
committed
Apply 0014-headers-compat.patch
1 parent dcfd960 commit fcc8144

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11 files changed

+586
-72
lines changed

11 files changed

+586
-72
lines changed

‎clang/lib/Headers/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ set(arm_only_files
5151

5252
set(aarch64_only_files
5353
arm64intr.h
54+
arm64_neon.h
5455
arm_neon_sve_bridge.h
5556
)
5657

‎clang/lib/Headers/arm64_neon.h‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,21 @@
1+
/*===---- arm64_neon.h - ARM Windows intrinsics ----------------------------===
2+
*
3+
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
* See https://llvm.org/LICENSE.txt for license information.
5+
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
*
7+
*===-----------------------------------------------------------------------===
8+
*/
9+
10+
/* Only include this if we're compiling for the windows platform. */
11+
#ifndef _MSC_VER
12+
#include_next <arm64_neon.h>
13+
#else
14+
15+
#ifndef __ARM64_NEON_H
16+
#define __ARM64_NEON_H
17+
18+
#include <arm_neon.h>
19+
20+
#endif /* __ARM64_NEON_H */
21+
#endif /* _MSC_VER */

‎clang/lib/Headers/arm64intr.h‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,16 @@
1515
#ifndef __ARM64INTR_H
1616
#define __ARM64INTR_H
1717

18+
#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
19+
( ((op0 & 1) << 14) | \
20+
((op1 & 7) << 11) | \
21+
((crn & 15) << 7) | \
22+
((crm & 15) << 3) | \
23+
((op2 & 7) << 0) )
24+
25+
#define ARM64_FPCR ARM64_SYSREG(3, 3, 4, 4, 0) // Floating point control register (EL0)
26+
#define ARM64_FPSR ARM64_SYSREG(3, 3, 4, 4, 1) // Floating point status register (EL0)
27+
1828
typedef enum
1929
{
2030
_ARM64_BARRIER_SY = 0xF,
@@ -31,5 +41,73 @@ typedef enum
3141
_ARM64_BARRIER_OSHLD = 0x1
3242
} _ARM64INTR_BARRIER_TYPE;
3343

44+
#if defined(__cplusplus)
45+
extern "C" {
46+
#endif
47+
48+
void __dmb(unsigned int _Type);
49+
void __dsb(unsigned int _Type);
50+
void __isb(unsigned int _Type);
51+
52+
unsigned __int8 __ldar8(unsigned __int8 volatile * _Target);
53+
unsigned __int16 __ldar16(unsigned __int16 volatile * _Target);
54+
unsigned __int32 __ldar32(unsigned __int32 volatile * _Target);
55+
unsigned __int64 __ldar64(unsigned __int64 volatile * _Target);
56+
57+
unsigned __int8 __ldapr8(unsigned __int8 volatile * _Target);
58+
unsigned __int16 __ldapr16(unsigned __int16 volatile * _Target);
59+
unsigned __int32 __ldapr32(unsigned __int32 volatile * _Target);
60+
unsigned __int64 __ldapr64(unsigned __int64 volatile * _Target);
61+
62+
unsigned __int8 __load_acquire8(unsigned __int8 volatile * _Target);
63+
unsigned __int16 __load_acquire16(unsigned __int16 volatile * _Target);
64+
unsigned __int32 __load_acquire32(unsigned __int32 volatile * _Target);
65+
unsigned __int64 __load_acquire64(unsigned __int64 volatile * _Target);
66+
67+
void __stlr8(unsigned __int8 volatile * _Target, unsigned __int8 _Value);
68+
void __stlr16(unsigned __int16 volatile * _Target, unsigned __int16 _Value);
69+
void __stlr32(unsigned __int32 volatile * _Target, unsigned __int32 _Value);
70+
void __stlr64(unsigned __int64 volatile * _Target, unsigned __int64 _Value);
71+
72+
unsigned __int8 __swp8(unsigned __int8 volatile * _Target, unsigned __int8 _Value);
73+
unsigned __int16 __swp16(unsigned __int16 volatile * _Target, unsigned __int16 _Value);
74+
unsigned __int32 __swp32(unsigned __int32 volatile * _Target, unsigned __int32 _Value);
75+
unsigned __int64 __swp64(unsigned __int64 volatile * _Target, unsigned __int64 _Value);
76+
unsigned __int8 __swpa8(unsigned __int8 volatile * _Target, unsigned __int8 _Value);
77+
unsigned __int16 __swpa16(unsigned __int16 volatile * _Target, unsigned __int16 _Value);
78+
unsigned __int32 __swpa32(unsigned __int32 volatile * _Target, unsigned __int32 _Value);
79+
unsigned __int64 __swpa64(unsigned __int64 volatile * _Target, unsigned __int64 _Value);
80+
unsigned __int8 __swpl8(unsigned __int8 volatile * _Target, unsigned __int8 _Value);
81+
unsigned __int16 __swpl16(unsigned __int16 volatile * _Target, unsigned __int16 _Value);
82+
unsigned __int32 __swpl32(unsigned __int32 volatile * _Target, unsigned __int32 _Value);
83+
unsigned __int64 __swpl64(unsigned __int64 volatile * _Target, unsigned __int64 _Value);
84+
unsigned __int8 __swpal8(unsigned __int8 volatile * _Target, unsigned __int8 _Value);
85+
unsigned __int16 __swpal16(unsigned __int16 volatile * _Target, unsigned __int16 _Value);
86+
unsigned __int32 __swpal32(unsigned __int32 volatile * _Target, unsigned __int32 _Value);
87+
unsigned __int64 __swpal64(unsigned __int64 volatile * _Target, unsigned __int64 _Value);
88+
89+
unsigned __int8 __cas8(unsigned __int8 volatile * _Target, unsigned __int8 _Comp, unsigned __int8 _Value);
90+
unsigned __int16 __cas16(unsigned __int16 volatile * _Target, unsigned __int16 _Comp, unsigned __int16 _Value);
91+
unsigned __int32 __cas32(unsigned __int32 volatile * _Target, unsigned __int32 _Comp, unsigned __int32 _Value);
92+
unsigned __int64 __cas64(unsigned __int64 volatile * _Target, unsigned __int64 _Comp, unsigned __int64 _Value);
93+
unsigned __int8 __casa8(unsigned __int8 volatile * _Target, unsigned __int8 _Comp, unsigned __int8 _Value);
94+
unsigned __int16 __casa16(unsigned __int16 volatile * _Target, unsigned __int16 _Comp, unsigned __int16 _Value);
95+
unsigned __int32 __casa32(unsigned __int32 volatile * _Target, unsigned __int32 _Comp, unsigned __int32 _Value);
96+
unsigned __int64 __casa64(unsigned __int64 volatile * _Target, unsigned __int64 _Comp, unsigned __int64 _Value);
97+
unsigned __int8 __casl8(unsigned __int8 volatile * _Target, unsigned __int8 _Comp, unsigned __int8 _Value);
98+
unsigned __int16 __casl16(unsigned __int16 volatile * _Target, unsigned __int16 _Comp, unsigned __int16 _Value);
99+
unsigned __int32 __casl32(unsigned __int32 volatile * _Target, unsigned __int32 _Comp, unsigned __int32 _Value);
100+
unsigned __int64 __casl64(unsigned __int64 volatile * _Target, unsigned __int64 _Comp, unsigned __int64 _Value);
101+
unsigned __int8 __casal8(unsigned __int8 volatile * _Target, unsigned __int8 _Comp, unsigned __int8 _Value);
102+
unsigned __int16 __casal16(unsigned __int16 volatile * _Target, unsigned __int16 _Comp, unsigned __int16 _Value);
103+
unsigned __int32 __casal32(unsigned __int32 volatile * _Target, unsigned __int32 _Comp, unsigned __int32 _Value);
104+
unsigned __int64 __casal64(unsigned __int64 volatile * _Target, unsigned __int64 _Comp, unsigned __int64 _Value);
105+
106+
#ifdef __cplusplus
107+
}
108+
#endif
109+
110+
#include <arm_acle.h>
111+
34112
#endif /* __ARM64INTR_H */
35113
#endif /* _MSC_VER */

‎clang/lib/Headers/cetintrin.h‎

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -51,11 +51,7 @@ static __inline__ unsigned int __DEFAULT_FN_ATTRS _rdsspd_i32(void) {
5151
}
5252

5353
#ifdef __x86_64__
54-
static __inline__ unsigned long long __DEFAULT_FN_ATTRS _rdsspq(unsigned long long __a) {
55-
return __builtin_ia32_rdsspq(__a);
56-
}
57-
58-
static __inline__ unsigned long long __DEFAULT_FN_ATTRS _rdsspq_i64(void) {
54+
static __inline__ unsigned long long __DEFAULT_FN_ATTRS _rdsspq(void) {
5955
#pragma clang diagnostic push
6056
#pragma clang diagnostic ignored "-Wuninitialized"
6157
unsigned long long t;
@@ -82,6 +78,14 @@ static __inline__ void __DEFAULT_FN_ATTRS _rstorssp(void * __p) {
8278
__builtin_ia32_rstorssp(__p);
8379
}
8480

81+
static __inline__ void * __DEFAULT_FN_ATTRS _switchssp(void *__local_stack) {
82+
void * prev_stack;
83+
prev_stack = (void *) _rdsspq();
84+
__builtin_ia32_rstorssp(__local_stack);
85+
__builtin_ia32_saveprevssp();
86+
return prev_stack;
87+
}
88+
8589
static __inline__ void __DEFAULT_FN_ATTRS _wrssd(unsigned int __a, void * __p) {
8690
__builtin_ia32_wrssd(__a, __p);
8791
}

‎clang/lib/Headers/fxsrintrin.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,9 @@ _fxsave(void *__p)
4545
/// A pointer to a 512-byte memory region. The beginning of this memory
4646
/// region should be aligned on a 16-byte boundary.
4747
static __inline__ void __DEFAULT_FN_ATTRS
48-
_fxrstor(void *__p)
48+
_fxrstor(void const *__p)
4949
{
50-
__builtin_ia32_fxrstor(__p);
50+
__builtin_ia32_fxrstor((void *) __p);
5151
}
5252

5353
#ifdef __x86_64__
@@ -80,9 +80,9 @@ _fxsave64(void *__p)
8080
/// A pointer to a 512-byte memory region. The beginning of this memory
8181
/// region should be aligned on a 16-byte boundary.
8282
static __inline__ void __DEFAULT_FN_ATTRS
83-
_fxrstor64(void *__p)
83+
_fxrstor64(void const *__p)
8484
{
85-
__builtin_ia32_fxrstor64(__p);
85+
__builtin_ia32_fxrstor64((void *)__p);
8686
}
8787
#endif
8888

‎clang/lib/Headers/ia32intrin.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -534,7 +534,7 @@ __rdtscp(unsigned int *__A) {
534534
#define _rdpmc(A) __rdpmc(A)
535535

536536
static __inline__ void __DEFAULT_FN_ATTRS
537-
_wbinvd(void) {
537+
__wbinvd(void) {
538538
__builtin_ia32_wbinvd();
539539
}
540540

‎clang/lib/Headers/immintrin.h‎

Lines changed: 97 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -303,6 +303,103 @@ _writegsbase_u64(unsigned long long __V)
303303
__builtin_ia32_wrgsbase64(__V);
304304
}
305305

306+
// REVIEW: Decide if upgrade to builtins
307+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
308+
__writegsbyte(unsigned long __offset,unsigned char __data) {
309+
__asm__ volatile ("movb %0,%%gs:%c1"
310+
: : "ir"(__data), "ir"(__offset) : "memory");
311+
}
312+
313+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
314+
__writegsword(unsigned long __offset,unsigned short __data) {
315+
__asm__ volatile ("movw %0,%%gs:%c1"
316+
: : "ir"(__data), "ir"(__offset) : "memory");
317+
}
318+
319+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
320+
__writegsdword(unsigned long __offset,unsigned long __data) {
321+
__asm__ volatile ("movl %0,%%gs:%c1"
322+
: : "ir"(__data), "ir"(__offset) : "memory");
323+
}
324+
325+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
326+
__writegsqword(unsigned long __offset,unsigned __int64 __data) {
327+
__asm__ volatile ("movq %0,%%gs:%c1"
328+
: : "ir"(__data), "ir"(__offset) : "memory");
329+
}
330+
331+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
332+
__addgsbyte(unsigned long __offset, unsigned char __data) {
333+
__asm__ __volatile__ (
334+
"addb %1, %%gs:(%c0)"
335+
:
336+
: "ir"(__offset), "ir"(__data)
337+
: "memory");
338+
}
339+
340+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
341+
__addgsword(unsigned long __offset, unsigned short __data) {
342+
__asm__ __volatile__ (
343+
"addw %1, %%gs:(%c0)"
344+
:
345+
: "ir"(__offset), "ir"(__data)
346+
: "memory");
347+
}
348+
349+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
350+
__addgsdword(unsigned long __offset, unsigned long __data) {
351+
__asm__ __volatile__ (
352+
"addl %1, %%gs:(%c0)"
353+
:
354+
: "ir"(__offset), "ir"(__data)
355+
: "memory");
356+
}
357+
358+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
359+
__addgsqword(unsigned long __offset, unsigned __int64 __data) {
360+
__asm__ __volatile__ (
361+
"add %1, %%gs:(%c0)"
362+
:
363+
: "ir"(__offset), "ir"(__data)
364+
: "memory");
365+
}
366+
367+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
368+
__incgsbyte(unsigned long __offset) {
369+
__asm__ __volatile__ (
370+
"incb %%gs:(%c0)"
371+
:
372+
: "ir"(__offset)
373+
: "memory");
374+
}
375+
376+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
377+
__incgsword(unsigned long __offset) {
378+
__asm__ __volatile__ (
379+
"incw %%gs:(%c0)"
380+
:
381+
: "ir"(__offset)
382+
: "memory");
383+
}
384+
385+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
386+
__incgsdword(unsigned long __offset) {
387+
__asm__ __volatile__ (
388+
"incl %%gs:(%c0)"
389+
:
390+
: "ir"(__offset)
391+
: "memory");
392+
}
393+
394+
static __inline__ void __attribute__((__always_inline__, __nodebug__, __target__("fsgsbase")))
395+
__incgsqword(unsigned long __offset) {
396+
__asm__ __volatile__ (
397+
"inc %%gs:(%c0)"
398+
:
399+
: "ir"(__offset)
400+
: "memory");
401+
}
402+
306403
#endif
307404

308405
/* The structs used below are to force the load/store to be unaligned. This

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