updating all the slow than 25Gb/s target to automatically disable QSFP in FW without SW

ruck314 · ruck314 · commit 27f2c1d128bd · 2025-04-30T18:58:08.000-07:00
diff --git a/firmware/submodules/axi-pcie-core b/firmware/submodules/axi-pcie-core
@@ -1 +1 @@
-Subproject commit b0bb9badacad4f9e8f6fbbd16750ff1d22a66292
+Subproject commit bccc46cb26a1d25eb519f9611d60e9418d6365da
diff --git a/firmware/submodules/ruckus b/firmware/submodules/ruckus
@@ -1 +1 @@
-Subproject commit f124fca0687c3f537b3308b9d77948d5a266b294
+Subproject commit 507370483c54d4c08e44e5bf912255963df79fd5
diff --git a/firmware/submodules/surf b/firmware/submodules/surf
@@ -1 +1 @@
-Subproject commit d1188e85496a60562c49618d127cec61c7fa806b
+Subproject commit df0907273b40a181af08f82899285c5255af71b3
diff --git a/firmware/targets/XilinxAlveoU55c/XilinxAlveoU55cDmaLoopback/hdl/XilinxAlveoU55cDmaLoopback.vhd b/firmware/targets/XilinxAlveoU55c/XilinxAlveoU55cDmaLoopback/hdl/XilinxAlveoU55cDmaLoopback.vhd
@@ -133,10 +133,11 @@ begin
 
    U_Core : entity axi_pcie_core.XilinxAlveoU55cCore
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
@@ -160,11 +161,11 @@ begin
          --  Core Ports
          --------------
          -- Card Management Solution (CMS) Interface
-         cmsHbmCatTrip   => cmsHbmCatTrip,
-         cmsHbmTemp      => cmsHbmTemp,
-         cmsUartRxd      => cmsUartRxd,
-         cmsUartTxd      => cmsUartTxd,
-         cmsGpio         => cmsGpio,
+         cmsHbmCatTrip  => cmsHbmCatTrip,
+         cmsHbmTemp     => cmsHbmTemp,
+         cmsUartRxd     => cmsUartRxd,
+         cmsUartTxd     => cmsUartTxd,
+         cmsGpio        => cmsGpio,
          -- System Ports
          userClkP       => userClkP,
          userClkN       => userClkN,
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/hdl/XilinxVariumC1100DmaLoopback.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopback/hdl/XilinxVariumC1100DmaLoopback.vhd
@@ -133,10 +133,11 @@ begin
 
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopbackBifurcatedPcie/hdl/XilinxVariumC1100DmaLoopbackBifurcatedPcie.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100DmaLoopbackBifurcatedPcie/hdl/XilinxVariumC1100DmaLoopbackBifurcatedPcie.vhd
@@ -107,10 +107,11 @@ begin
 
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp2b/hdl/XilinxVariumC1100Pgp2b.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp2b/hdl/XilinxVariumC1100Pgp2b.vhd
@@ -167,6 +167,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_10Gbps/hdl/XilinxVariumC1100Pgp4_10Gbps.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_10Gbps/hdl/XilinxVariumC1100Pgp4_10Gbps.vhd
@@ -169,6 +169,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps/hdl/XilinxVariumC1100Pgp4_15Gbps.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps/hdl/XilinxVariumC1100Pgp4_15Gbps.vhd
@@ -169,6 +169,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_6Gbps/hdl/XilinxVariumC1100Pgp4_6Gbps.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_6Gbps/hdl/XilinxVariumC1100Pgp4_6Gbps.vhd
@@ -169,6 +169,7 @@ begin
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
          TPD_G                => TPD_G,
+         QSFP_CDR_DISABLE_G   => true,
          ROGUE_SIM_EN_G       => ROGUE_SIM_EN_G,
          ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
          BUILD_INFO_G         => BUILD_INFO_G,
diff --git a/firmware/targets/XilinxVariumC1100/XilinxVariumC1100PrbsTester/hdl/XilinxVariumC1100PrbsTester.vhd b/firmware/targets/XilinxVariumC1100/XilinxVariumC1100PrbsTester/hdl/XilinxVariumC1100PrbsTester.vhd
@@ -127,10 +127,11 @@ begin
 
    U_Core : entity axi_pcie_core.XilinxVariumC1100Core
       generic map (
-         TPD_G             => TPD_G,
-         BUILD_INFO_G      => BUILD_INFO_G,
-         DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_C,
-         DMA_SIZE_G        => DMA_SIZE_C)
+         TPD_G              => TPD_G,
+         QSFP_CDR_DISABLE_G => true,
+         BUILD_INFO_G       => BUILD_INFO_G,
+         DMA_AXIS_CONFIG_G  => DMA_AXIS_CONFIG_C,
+         DMA_SIZE_G         => DMA_SIZE_C)
       port map (
          ------------------------
          --  Top Level Interfaces
diff --git a/firmware/targets/shared_config.mk b/firmware/targets/shared_config.mk
@@ -1,5 +1,5 @@
-# Define Firmware Version: v2.7.0.0
-export PRJ_VERSION = 0x02070000
+# Define Firmware Version: v2.8.0.0
+export PRJ_VERSION = 0x02080000
 
 # Define release
 ifndef RELEASE
