Commit 586133a
4 files changed
+5
-5
lines changedSubmodule axi-pcie-core updated 33 files
- hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.dcp+2-2
- hardware/AbacoPc821/pcie/ip/AbacoPc821PciePhy.xci+6-6
- hardware/AlphaDataKu3/pcie/ip/AlphaDataKu3PciePhy.dcp+2-2
- hardware/AlphaDataKu3/pcie/ip/AlphaDataKu3PciePhy.xci+19-15
- hardware/BittWareXupVv8/pcie/ip/BittWareXupVv8PciePhy.dcp+2-2
- hardware/BittWareXupVv8/pcie/ip/BittWareXupVv8PciePhy.xci+13-9
- hardware/SlacPgpCardG4/pcie/ip/XCKU040/SlacPgpCardG4PciePhy.dcp+2-2
- hardware/SlacPgpCardG4/pcie/ip/XCKU040/SlacPgpCardG4PciePhy.xci+8-5
- hardware/XilinxAlveoU200/pcie/ip/XilinxAlveoU200PciePhy.dcp+2-2
- hardware/XilinxAlveoU200/pcie/ip/XilinxAlveoU200PciePhy.xci+20-16
- hardware/XilinxAlveoU250/pcie/ip/XilinxAlveoU250PciePhy.dcp+2-2
- hardware/XilinxAlveoU250/pcie/ip/XilinxAlveoU250PciePhy.xci+20-16
- hardware/XilinxAlveoU280/pcie-3x16/ip/XilinxAlveoU280PciePhyGen3x16.dcp+2-2
- hardware/XilinxAlveoU280/pcie-3x16/ip/XilinxAlveoU280PciePhyGen3x16.xci+24-20
- hardware/XilinxAlveoU50/pcie-3x16/ip/XilinxAlveoU50PciePhyGen3x16.dcp+2-2
- hardware/XilinxAlveoU50/pcie-3x16/ip/XilinxAlveoU50PciePhyGen3x16.xci+9-9
- hardware/XilinxAlveoU55c/pcie-4x8/ip/XilinxAlveoU55cPciePhyGen4x8.dcp+2-2
- hardware/XilinxAlveoU55c/pcie-4x8/ip/XilinxAlveoU55cPciePhyGen4x8.xci+1.8k-2.4k
- hardware/XilinxKcu105/pcie/ip/XilinxKcu105PciePhy.dcp+2-2
- hardware/XilinxKcu105/pcie/ip/XilinxKcu105PciePhy.xci+15-12
- hardware/XilinxKcu116/pcie/ip/XilinxKcu116PciePhy.dcp+2-2
- hardware/XilinxKcu116/pcie/ip/XilinxKcu116PciePhy.xci+20-16
- hardware/XilinxKcu1500/pcie-extended/ip/XilinxKcu1500ExtendedPciePhy.dcp+2-2
- hardware/XilinxKcu1500/pcie-extended/ip/XilinxKcu1500ExtendedPciePhy.xci+15-12
- hardware/XilinxKcu1500/pcie/ip/XilinxKcu1500PciePhy.dcp+2-2
- hardware/XilinxKcu1500/pcie/ip/XilinxKcu1500PciePhy.xci+15-12
- hardware/XilinxVariumC1100/pcie-4x8/ip/XilinxVariumC1100PciePhyGen4x8.dcp+2-2
- hardware/XilinxVariumC1100/pcie-4x8/ip/XilinxVariumC1100PciePhyGen4x8.xci+16-16
- hardware/XilinxVariumC1100/pcie-extended/ip/XilinxVariumC1100ExtendedPciePhy.dcp+2-2
- hardware/XilinxVariumC1100/pcie-extended/ip/XilinxVariumC1100ExtendedPciePhy.xci+14-14
- hardware/XilinxVcu128/pcie-3x16/ip/XilinxVcu128PciePhyGen3x16.dcp+2-2
- hardware/XilinxVcu128/pcie-3x16/ip/XilinxVcu128PciePhyGen3x16.xci+13-9
- python/axipcie/_AxiPcieCore.py+44-18
- axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd+290
- axi/axi-stream/rtl/AxiStreamTimer.vhd+246
- axi/axi-stream/tb/AxiStreamBatchingFifoTb.vhd+142
- dsp/generic/fixed/FirFilterSingleChannel.vhd+116-58
- dsp/generic/tb/FirFilterSingleChannelTb.vhd+5-4
- ethernet/GigEthCore/lvdsUltraScale/ruckus.tcl+2-2
- protocols/htsp/core/rtl/HtspAxiL.vhd+27
- protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd+42
- protocols/pgp/pgp4/core/rtl/Pgp4CoreLite.vhd+44-28
- python/surf/axi/_AxiStreamBatchingFifo.py+23
- python/surf/axi/_AxiStreamTimer.py+69
- python/surf/axi/__init__.py+2-1
- python/surf/protocols/htsp/_HtspAxiL.py+72
- python/surf/protocols/pgp/_Pgp4AxiL.py+82
- tests/test_AxiStreamBatchingFifoTb.py+111
- xilinx/general/microblaze/ruckus.tcl+10-5
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