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ruck314ruck314
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adding dynamic rx/tx polarity configuration support to PGP4
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‎firmware/submodules/ruckus‎

‎firmware/submodules/surf‎

Submodule surf updated 91 files

‎firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps/vivado/post_synthesis.tcl‎

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##############################################################################
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## This file is part of 'PGP PCIe APP DEV'.
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## It is subject to the license terms in the LICENSE.txt file found in the
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## top-level directory of this distribution and at:
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## https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
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## No part of 'PGP PCIe APP DEV', including this file,
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## may be copied, modified, propagated, or distributed except according to
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## the terms contained in the LICENSE.txt file.
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##############################################################################
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##############################
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# Get variables and procedures
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##############################
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source -quiet $::env(RUCKUS_DIR)/vivado_env_var.tcl
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source $::env(RUCKUS_PROC_TCL)
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######################################################
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# Bypass the debug chipscope generation via return cmd
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# ELSE ... comment out the return to include chipscope
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######################################################
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return
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############################
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## Open the synthesis design
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############################
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open_run synth_1
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###############################
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## Set the name of the ILA core
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###############################
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set ilaName u_ila_0
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##################
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## Create the core
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##################
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CreateDebugCore ${ilaName}
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#######################
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## Set the record depth
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#######################
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set_property C_DATA_DEPTH 1024 [get_debug_cores ${ilaName}]
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#################################
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## Set the clock for the ILA core
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#################################
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SetDebugCoreClk ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxClk}
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#######################
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## Set the debug Probes
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#######################
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxRst}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxSlip}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxValid}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxActive}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxData[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/phyRxHeader[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/unscrambledData[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/unscrambledHeader[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/unscrambledValid}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/unscramblerValid}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp3RxGearboxAligner_1/locked}
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##########################
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## Write the port map file
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##########################
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WriteDebugProbes ${ilaName}
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###############################
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## Set the name of the ILA core
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###############################
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set ilaName u_ila_1
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##################
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## Create the core
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##################
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CreateDebugCore ${ilaName}
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#######################
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## Set the record depth
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#######################
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set_property C_DATA_DEPTH 1024 [get_debug_cores ${ilaName}]
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#################################
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## Set the clock for the ILA core
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#################################
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SetDebugCoreClk ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxClk}
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#######################
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## Set the debug Probes
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#######################
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxMaster[tData][*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxMaster[tUser][*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/protRxData[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/protRxHeader[*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/r_reg[count][*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/r_reg[notValidCnt][*]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/eof}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/linkError}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxIn[resetRx]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxMaster[tLast]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxMaster[tValid]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxOut[linkReady]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxOut[opCodeEn]}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/pgpRxRst}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/phyRxActive}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/phyRxActiveSync}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/phyRxActiveSyncFall}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/protRxPhyInit}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/protRxValid}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/remRxLinkReady}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/U_Pgp4RxProtocol_1/sof}
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ConfigProbe ${ilaName} {U_Hardware/U_Pgp/GEN_LANE[0].U_Lane/U_Pgp/U_Pgp4Core_1/GEN_RX.U_Pgp4Rx_1/ebValid}
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##########################
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## Write the port map file
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##########################
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WriteDebugProbes ${ilaName}

‎firmware/targets/shared_config.mk‎

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# Define Firmware Version: v2.10.0.0
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export PRJ_VERSION = 0x02100000
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# Define Firmware Version: v2.11.0.0
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export PRJ_VERSION = 0x02110000
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# Define release
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ifndef RELEASE

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