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adding PGPv4@13G support
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‎firmware/Makefile‎

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@@ -5,7 +5,6 @@ export TARGET_DIRS = $(PWD)/targets/SlacPgpCardG4/SlacPgpCardG4Pgp4_6Gbps \
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$(PWD)/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_6Gbps \
66
$(PWD)/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_10Gbps \
77
$(PWD)/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps \
8-
$(PWD)/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_18Gbps \
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$(PWD)/targets/XilinxVariumC1100/XilinxVariumC1100Htsp100GbpsBifurcatedPcie
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.PHONY: all build clean

‎firmware/releases.yaml‎

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@@ -76,10 +76,6 @@ Targets:
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ImageDir: targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps/images
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Extensions:
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- mcs
79-
XilinxVariumC1100Pgp4_18Gbps:
80-
ImageDir: targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_15Gbps/images
81-
Extensions:
82-
- mcs
8379
XilinxVariumC1100Htsp100GbpsBifurcatedPcie:
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ImageDir: targets/XilinxVariumC1100/XilinxVariumC1100Htsp100GbpsBifurcatedPcie/images
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Extensions:
@@ -107,7 +103,6 @@ Releases:
107103
- XilinxVariumC1100Pgp4_6Gbps
108104
- XilinxVariumC1100Pgp4_10Gbps
109105
- XilinxVariumC1100Pgp4_15Gbps
110-
- XilinxVariumC1100Pgp4_18Gbps
111106
- XilinxVariumC1100Htsp100GbpsBifurcatedPcie
112107
#######################################
113108
Types:

‎firmware/submodules/surf‎

‎firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_12Gbps/hdl/XilinxVariumC1100Pgp4_12Gbps.vhd‎

Lines changed: 1 addition & 1 deletion
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@@ -169,7 +169,7 @@ begin
169169
U_Core : entity axi_pcie_core.XilinxVariumC1100Core
170170
generic map (
171171
TPD_G => TPD_G,
172-
QSFP_CDR_DISABLE_G => false, -- FALSE: 25.78125Gbps/12.5Gbps = 2.0625 = 2 + 1/16
172+
QSFP_CDR_DISABLE_G => false, -- FALSE: 25G CDR does work with this line rate (within the QSFP's CDR margin)
173173
ROGUE_SIM_EN_G => ROGUE_SIM_EN_G,
174174
ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
175175
BUILD_INFO_G => BUILD_INFO_G,

‎firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_13Gbps/Makefile‎

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export PARALLEL_SYNTH = 8
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3+
# Define target part
4+
export PRJ_PART = XCU55N-FSVH2892-2L-E
5+
6+
# Define target output
7+
target: prom
8+
9+
# Using a non-standard target directory structure,
10+
# which requires me to define the TOP_DIR path
11+
export TOP_DIR = $(abspath $(PWD)/../../..)
12+
13+
# Use top level makefile
14+
include $(TOP_DIR)/targets/shared_config.mk
15+
include $(TOP_DIR)/submodules/ruckus/system_vivado.mk

‎firmware/targets/XilinxVariumC1100/XilinxVariumC1100Pgp4_13Gbps/hdl/XilinxVariumC1100Pgp4_13Gbps.vhd‎

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-------------------------------------------------------------------------------
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-- Company : SLAC National Accelerator Laboratory
3+
-------------------------------------------------------------------------------
4+
-- Description:
5+
-------------------------------------------------------------------------------
6+
-- This file is part of 'PGP PCIe APP DEV'.
7+
-- It is subject to the license terms in the LICENSE.txt file found in the
8+
-- top-level directory of this distribution and at:
9+
-- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
10+
-- No part of 'PGP PCIe APP DEV', including this file,
11+
-- may be copied, modified, propagated, or distributed except according to
12+
-- the terms contained in the LICENSE.txt file.
13+
-------------------------------------------------------------------------------
14+
15+
library ieee;
16+
use ieee.std_logic_1164.all;
17+
18+
library surf;
19+
use surf.StdRtlPkg.all;
20+
use surf.AxiPkg.all;
21+
use surf.AxiLitePkg.all;
22+
use surf.AxiStreamPkg.all;
23+
use surf.SsiPkg.all;
24+
use surf.Pgp4Pkg.all;
25+
26+
library axi_pcie_core;
27+
use axi_pcie_core.AxiPciePkg.all;
28+
29+
library unisim;
30+
use unisim.vcomponents.all;
31+
32+
entity XilinxVariumC1100Pgp4_13Gbps is
33+
generic (
34+
TPD_G : time := 1 ns;
35+
ROGUE_SIM_EN_G : boolean := false;
36+
ROGUE_SIM_PORT_NUM_G : natural range 1024 to 49151 := 8000;
37+
DMA_AXIS_CONFIG_G : AxiStreamConfigType := ssiAxiStreamConfig(dataBytes => 16, tDestBits => 8, tIdBits => 3); --- 16 Byte (128-bit) tData interface
38+
BUILD_INFO_G : BuildInfoType);
39+
port (
40+
---------------------
41+
-- Application Ports
42+
---------------------
43+
-- QSFP[0] Ports
44+
qsfp0RefClkP : in sl;
45+
qsfp0RefClkN : in sl;
46+
qsfp0RxP : in slv(3 downto 0);
47+
qsfp0RxN : in slv(3 downto 0);
48+
qsfp0TxP : out slv(3 downto 0);
49+
qsfp0TxN : out slv(3 downto 0);
50+
-- QSFP[1] Ports
51+
qsfp1RefClkP : in sl;
52+
qsfp1RefClkN : in sl;
53+
qsfp1RxP : in slv(3 downto 0);
54+
qsfp1RxN : in slv(3 downto 0);
55+
qsfp1TxP : out slv(3 downto 0);
56+
qsfp1TxN : out slv(3 downto 0);
57+
-- HBM Ports
58+
hbmCatTrip : out sl := '0'; -- HBM Catastrophic Over temperature Output signal to Satellite Controller: active HIGH indicator to Satellite controller to indicate the HBM has exceeds its maximum allowable temperature
59+
--------------
60+
-- Core Ports
61+
--------------
62+
-- Card Management Solution (CMS) Interface
63+
cmsUartRxd : in sl;
64+
cmsUartTxd : out sl;
65+
cmsGpio : in slv(3 downto 0);
66+
-- System Ports
67+
userClkP : in sl;
68+
userClkN : in sl;
69+
hbmRefClkP : in sl;
70+
hbmRefClkN : in sl;
71+
-- SI5394 Ports
72+
si5394Scl : inout sl;
73+
si5394Sda : inout sl;
74+
si5394IrqL : in sl;
75+
si5394LolL : in sl;
76+
si5394LosL : in sl;
77+
si5394RstL : out sl;
78+
-- PCIe Ports
79+
pciRstL : in sl;
80+
pciRefClkP : in slv(0 downto 0);
81+
pciRefClkN : in slv(0 downto 0);
82+
pciRxP : in slv(7 downto 0);
83+
pciRxN : in slv(7 downto 0);
84+
pciTxP : out slv(7 downto 0);
85+
pciTxN : out slv(7 downto 0));
86+
end XilinxVariumC1100Pgp4_13Gbps;
87+
88+
architecture top_level of XilinxVariumC1100Pgp4_13Gbps is
89+
90+
constant AXIL_XBAR_CONFIG_C : AxiLiteCrossbarMasterConfigArray(4 downto 0) := (
91+
0 => (
92+
baseAddr => x"0010_0000",
93+
addrBits => 20,
94+
connectivity => x"FFFF"),
95+
1 => (
96+
baseAddr => x"0020_0000",
97+
addrBits => 20,
98+
connectivity => x"FFFF"),
99+
2 => (
100+
baseAddr => x"0030_0000",
101+
addrBits => 20,
102+
connectivity => x"FFFF"),
103+
3 => (
104+
baseAddr => x"0040_0000",
105+
addrBits => 20,
106+
connectivity => x"FFFF"),
107+
4 => (
108+
baseAddr => x"0080_0000",
109+
addrBits => 23,
110+
connectivity => x"FFFF"));
111+
112+
signal axilClk : sl;
113+
signal axilRst : sl;
114+
signal axilReadMaster : AxiLiteReadMasterType;
115+
signal axilReadSlave : AxiLiteReadSlaveType;
116+
signal axilWriteMaster : AxiLiteWriteMasterType;
117+
signal axilWriteSlave : AxiLiteWriteSlaveType;
118+
119+
signal axilReadMasters : AxiLiteReadMasterArray(4 downto 0);
120+
signal axilReadSlaves : AxiLiteReadSlaveArray(4 downto 0) := (others => AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C);
121+
signal axilWriteMasters : AxiLiteWriteMasterArray(4 downto 0);
122+
signal axilWriteSlaves : AxiLiteWriteSlaveArray(4 downto 0) := (others => AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C);
123+
124+
signal dmaClk : sl;
125+
signal dmaRst : sl;
126+
signal dmaBuffGrpPause : slv(7 downto 0);
127+
signal dmaObMasters : AxiStreamMasterArray(7 downto 0);
128+
signal dmaObSlaves : AxiStreamSlaveArray(7 downto 0);
129+
signal dmaIbMasters : AxiStreamMasterArray(7 downto 0);
130+
signal dmaIbSlaves : AxiStreamSlaveArray(7 downto 0);
131+
signal buffIbMasters : AxiStreamMasterArray(7 downto 0);
132+
signal buffIbSlaves : AxiStreamSlaveArray(7 downto 0);
133+
134+
signal hbmRefClk : sl;
135+
signal userClk : sl;
136+
137+
signal eventTrigMsgCtrl : AxiStreamCtrlArray(7 downto 0) := (others => AXI_STREAM_CTRL_UNUSED_C);
138+
signal pgpClkOut : slv(7 downto 0);
139+
signal pgpTxIn : Pgp4TxInArray(7 downto 0) := (others => PGP4_TX_IN_INIT_C);
140+
141+
signal cmsHbmCatTrip : sl := '0';
142+
signal cmsHbmTemp : Slv7Array(1 downto 0) := (others => b"0000000");
143+
144+
begin
145+
146+
U_axilClk : entity surf.ClockManagerUltraScale
147+
generic map(
148+
TPD_G => TPD_G,
149+
TYPE_G => "MMCM",
150+
INPUT_BUFG_G => true,
151+
FB_BUFG_G => true,
152+
RST_IN_POLARITY_G => '1',
153+
NUM_CLOCKS_G => 1,
154+
-- MMCM attributes
155+
BANDWIDTH_G => "OPTIMIZED",
156+
CLKIN_PERIOD_G => 10.0, -- 100MHz
157+
DIVCLK_DIVIDE_G => 8, -- 12.5MHz = 100MHz/8
158+
CLKFBOUT_MULT_F_G => 96.875, -- 1210.9375MHz = 96.875 x 12.5MHz
159+
CLKOUT0_DIVIDE_F_G => 7.75) -- 156.25MHz = 1210.9375MHz/7.75
160+
port map(
161+
-- Clock Input
162+
clkIn => userClk,
163+
rstIn => dmaRst,
164+
-- Clock Outputs
165+
clkOut(0) => axilClk,
166+
-- Reset Outputs
167+
rstOut(0) => axilRst);
168+
169+
U_Core : entity axi_pcie_core.XilinxVariumC1100Core
170+
generic map (
171+
TPD_G => TPD_G,
172+
QSFP_CDR_DISABLE_G => false, -- FALSE: 25G CDR does work with this line rate (within the QSFP's CDR margin)
173+
ROGUE_SIM_EN_G => ROGUE_SIM_EN_G,
174+
ROGUE_SIM_PORT_NUM_G => ROGUE_SIM_PORT_NUM_G,
175+
BUILD_INFO_G => BUILD_INFO_G,
176+
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
177+
DMA_SIZE_G => 8)
178+
port map (
179+
------------------------
180+
-- Top Level Interfaces
181+
------------------------
182+
userClk => userClk,
183+
hbmRefClk => hbmRefClk,
184+
-- DMA Interfaces
185+
dmaClk => dmaClk,
186+
dmaRst => dmaRst,
187+
dmaBuffGrpPause => dmaBuffGrpPause,
188+
dmaObMasters => dmaObMasters,
189+
dmaObSlaves => dmaObSlaves,
190+
dmaIbMasters => dmaIbMasters,
191+
dmaIbSlaves => dmaIbSlaves,
192+
-- Application AXI-Lite Interfaces [0x00100000:0x00FFFFFF]
193+
appClk => axilClk,
194+
appRst => axilRst,
195+
appReadMaster => axilReadMaster,
196+
appReadSlave => axilReadSlave,
197+
appWriteMaster => axilWriteMaster,
198+
appWriteSlave => axilWriteSlave,
199+
--------------
200+
-- Core Ports
201+
--------------
202+
-- Card Management Solution (CMS) Interface
203+
cmsHbmCatTrip => cmsHbmCatTrip,
204+
cmsHbmTemp => cmsHbmTemp,
205+
cmsUartRxd => cmsUartRxd,
206+
cmsUartTxd => cmsUartTxd,
207+
cmsGpio => cmsGpio,
208+
-- System Ports
209+
userClkP => userClkP,
210+
userClkN => userClkN,
211+
hbmRefClkP => hbmRefClkP,
212+
hbmRefClkN => hbmRefClkN,
213+
-- SI5394 Ports
214+
si5394Scl => si5394Scl,
215+
si5394Sda => si5394Sda,
216+
si5394IrqL => si5394IrqL,
217+
si5394LolL => si5394LolL,
218+
si5394LosL => si5394LosL,
219+
si5394RstL => si5394RstL,
220+
-- PCIe Ports
221+
pciRstL => pciRstL,
222+
pciRefClkP => pciRefClkP,
223+
pciRefClkN => pciRefClkN,
224+
pciRxP => pciRxP,
225+
pciRxN => pciRxN,
226+
pciTxP => pciTxP,
227+
pciTxN => pciTxN);
228+
229+
--------------------
230+
-- AXI-Lite Crossbar
231+
--------------------
232+
U_XBAR : entity surf.AxiLiteCrossbar
233+
generic map (
234+
TPD_G => TPD_G,
235+
NUM_SLAVE_SLOTS_G => 1,
236+
NUM_MASTER_SLOTS_G => 5,
237+
MASTERS_CONFIG_G => AXIL_XBAR_CONFIG_C)
238+
port map (
239+
axiClk => axilClk,
240+
axiClkRst => axilRst,
241+
sAxiWriteMasters(0) => axilWriteMaster,
242+
sAxiWriteSlaves(0) => axilWriteSlave,
243+
sAxiReadMasters(0) => axilReadMaster,
244+
sAxiReadSlaves(0) => axilReadSlave,
245+
mAxiWriteMasters => axilWriteMasters,
246+
mAxiWriteSlaves => axilWriteSlaves,
247+
mAxiReadMasters => axilReadMasters,
248+
mAxiReadSlaves => axilReadSlaves);
249+
250+
----------------------------
251+
-- DMA Inbound Large Buffer
252+
----------------------------
253+
U_HbmDmaBuffer : entity axi_pcie_core.HbmDmaBuffer
254+
generic map (
255+
TPD_G => TPD_G,
256+
DMA_SIZE_G => 8,
257+
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G,
258+
CLKFBOUT_MULT_G => 10, -- 1.0GHz = 10 x 100 MHz
259+
CLKOUT0_DIVIDE_G => 4, -- 250MHz = 1.0GHz/4
260+
AXIL_BASE_ADDR_G => AXIL_XBAR_CONFIG_C(0).baseAddr)
261+
port map (
262+
-- Card Management Solution (CMS) Interface
263+
cmsHbmCatTrip => cmsHbmCatTrip,
264+
cmsHbmTemp => cmsHbmTemp,
265+
-- HBM Interface
266+
userClk => userClk,
267+
hbmRefClk => hbmRefClk,
268+
hbmCatTrip => hbmCatTrip,
269+
-- AXI-Lite Interface (axilClk domain)
270+
axilClk => axilClk,
271+
axilRst => axilRst,
272+
axilReadMaster => axilReadMasters(0),
273+
axilReadSlave => axilReadSlaves(0),
274+
axilWriteMaster => axilWriteMasters(0),
275+
axilWriteSlave => axilWriteSlaves(0),
276+
-- Trigger Event streams (eventClk domain)
277+
eventClk => pgpClkOut,
278+
eventTrigMsgCtrl => eventTrigMsgCtrl,
279+
-- AXI Stream Interface (axisClk domain)
280+
axisClk => (others => dmaClk),
281+
axisRst => (others => dmaRst),
282+
sAxisMasters => buffIbMasters,
283+
sAxisSlaves => buffIbSlaves,
284+
mAxisMasters => dmaIbMasters,
285+
mAxisSlaves => dmaIbSlaves);
286+
287+
GEN_LANE : for i in 7 downto 0 generate
288+
pgpTxIn(i).locData(0) <= eventTrigMsgCtrl(i).pause;
289+
end generate;
290+
291+
U_Hardware : entity work.Hardware
292+
generic map (
293+
TPD_G => TPD_G,
294+
RATE_G => "13.75Gbps",
295+
DMA_AXIS_CONFIG_G => DMA_AXIS_CONFIG_G)
296+
port map (
297+
------------------------
298+
-- Top Level Interfaces
299+
------------------------
300+
-- AXI-Lite Interface (axilClk domain)
301+
axilClk => axilClk,
302+
axilRst => axilRst,
303+
axilReadMaster => axilReadMasters(4),
304+
axilReadSlave => axilReadSlaves(4),
305+
axilWriteMaster => axilWriteMasters(4),
306+
axilWriteSlave => axilWriteSlaves(4),
307+
-- DMA Interface (dmaClk domain)
308+
dmaClk => dmaClk,
309+
dmaRst => dmaRst,
310+
dmaBuffGrpPause => dmaBuffGrpPause,
311+
dmaObMasters => dmaObMasters,
312+
dmaObSlaves => dmaObSlaves,
313+
dmaIbMasters => buffIbMasters,
314+
dmaIbSlaves => buffIbSlaves,
315+
-- Non-VC Interface (pgpClkOut domain)
316+
pgpClkOut => pgpClkOut,
317+
pgpTxIn => pgpTxIn,
318+
------------------
319+
-- Hardware Ports
320+
------------------
321+
-- QSFP[0] Ports
322+
qsfp0RefClkP => qsfp0RefClkP,
323+
qsfp0RefClkN => qsfp0RefClkN,
324+
qsfp0RxP => qsfp0RxP,
325+
qsfp0RxN => qsfp0RxN,
326+
qsfp0TxP => qsfp0TxP,
327+
qsfp0TxN => qsfp0TxN,
328+
-- QSFP[1] Ports
329+
qsfp1RefClkP => qsfp1RefClkP,
330+
qsfp1RefClkN => qsfp1RefClkN,
331+
qsfp1RxP => qsfp1RxP,
332+
qsfp1RxN => qsfp1RxN,
333+
qsfp1TxP => qsfp1TxP,
334+
qsfp1TxN => qsfp1TxN);
335+
336+
end top_level;

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