Find writeback registers (capstone-engine#2960)

Detection of writebacks was only partially implemented:
- MCInst_handleWriteback() was not called, so tied_op_idx was not filled
- map_get_op_access() in RISCV_add_cs_detail_0() queried tied_op_idx
  unnecessarily, because all elements were -1 (initialization value)

Author: slate5

arch/RISCV/RISCVDisassembler.c

@@ -748,6 +748,11 @@ bool RISCV_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
 {
 	RISCV_init_cs_detail(MI);
 	MI->MRI = (MCRegisterInfo *)Info;
-	return RISCV_getInstruction(MI, Size, Bytes, ByteLen, Address, NULL) !=
-	       MCDisassembler_Fail;
+	DecodeStatus ret =
+		RISCV_getInstruction(MI, Size, Bytes, ByteLen, Address, NULL);
+
+	MCInst_handleWriteback(MI, RISCVDescs.Insts,
+			       ARR_SIZE(RISCVDescs.Insts));
+
+	return ret != MCDisassembler_Fail;
 }

arch/RISCV/RISCVInstPrinter.c

@@ -424,7 +424,6 @@ void RISCV_LLVM_printInstruction(MCInst *MI, SStream *O,
 			printInstruction(McInstr, MI->address, O);
 	}
 	RISCV_add_groups(MI);
-	RISCV_add_missing_write_access(MI);
 	RISCV_compact_operands(MI);
 	RISCV_set_alias_id(MI, O);
 }

arch/RISCV/RISCVMapping.c

@@ -297,29 +297,6 @@ void RISCV_compact_operands(MCInst *MI)
 	       (NUM_RISCV_OPS - write_pos) * sizeof(cs_riscv_op));
 }
 
-// some RISC-V instructions have only 2 apparent operands, one of them is read-write
-// the actual operand information for those instruction should have 3 operands, the first and second are the same operand,
-// but once with read and once write access
-// when those instructions are disassembled only the operand entry with the read access is used,
-// and therefore the read-write operand is wrongly classified as only-read
-// this logic tries to correct that
-void RISCV_add_missing_write_access(MCInst *MI)
-{
-	if (!detail_is_set(MI))
-		return;
-	if (!isCompressed(MI))
-		return;
-
-	cs_riscv *riscv_details = RISCV_get_detail(MI);
-	cs_riscv_op *ops = riscv_details->operands;
-	// make the detection condition as specific as possible
-	// so it doesn't accidentally trigger for other cases
-	if (riscv_details->op_count == 2 && ops[0].type == RISCV_OP_INVALID &&
-	    ops[1].type == RISCV_OP_REG && ops[1].access == CS_AC_READ) {
-		ops[1].access |= CS_AC_WRITE;
-	}
-}
-
 // given internal insn id, return public instruction info
 void RISCV_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
 {

arch/RISCV/RISCVMapping.h

@@ -31,8 +31,6 @@ void RISCV_init_cs_detail(MCInst *MI);
 
 void RISCV_compact_operands(MCInst *MI);
 
-void RISCV_add_missing_write_access(MCInst *MI);
-
 // map instruction name to instruction ID
 riscv_insn RISCV_map_insn(const char *name);