Merge branch 'openwrt:main' into main

Author: small-white-rabbit

package/base-files/files/sbin/sysupgrade

@@ -146,7 +146,7 @@ list_conffiles() {
 		' /usr/lib/opkg/status
 	elif [ -d /lib/apk/packages ]; then
 		conffiles=""
-		for file in /lib/apk/packages/*.conffiles_static; do
+		for file in $(find /lib/apk/packages -name "*.conffiles_static" -type f); do
 			conffiles="$(echo -e "$(cat $file)\n$conffiles")"
 		done
 		echo "$conffiles"

package/kernel/mac80211/patches/ath9k/550-ath9k-of.patch

@@ -164,3 +164,26 @@
  	return 0;
  }
 
+--- a/drivers/net/wireless/ath/ath9k/hw.c
++++ b/drivers/net/wireless/ath/ath9k/hw.c
+@@ -2429,6 +2429,7 @@ static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
+ static void ath9k_gpio_cap_init(struct ath_hw *ah)
+ {
+ 	struct ath9k_hw_capabilities *pCap = &ah->caps;
++	u32 gpio_mask = pCap->gpio_mask;
+ 
+ 	if (AR_SREV_9271(ah)) {
+ 		pCap->num_gpio_pins = AR9271_NUM_GPIO;
+@@ -2479,6 +2480,12 @@ static void ath9k_gpio_cap_init(struct ath_hw *ah)
+ 		pCap->num_gpio_pins = AR_NUM_GPIO;
+ 		pCap->gpio_mask = AR_GPIO_MASK;
+ 	}
++
++	if (gpio_mask) {
++		pCap->gpio_mask = gpio_mask;
++		ath_info(ath9k_hw_common(ah), "Use overridden gpio mask 0x%x\n",
++			 gpio_mask);
++	}
+ }
+ 
+ int ath9k_hw_fill_cap_info(struct ath_hw *ah)

package/kernel/mt76/patches/0001-wifi-mt76-mt7915-set-mt76-specific-PS-flag.patch

@@ -136,7 +136,7 @@ ath79_setup_interfaces()
 		;;
 	airtight,c-75)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "2:wan" "3:lan" "6@eth1"
+			"0u@eth0" "2:wan" "3:lan" "6u@eth1"
 		;;
 	alfa-network,ap121fe)
 		ucidef_set_interface_lan "eth0 usb0"
@@ -200,7 +200,7 @@ ath79_setup_interfaces()
 	tplink,tl-wdr4900-v2|\
 	tplink,tl-wdr7500-v3)
 		ucidef_add_switch "switch0" \
-			"0@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth0" "1:wan"
+			"0u@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6u@eth0" "1:wan"
 		;;
 	buffalo,bhr-4grv|\
 	buffalo,wzr-hp-g450h)
@@ -210,11 +210,11 @@ ath79_setup_interfaces()
 	buffalo,bhr-4grv2|\
 	trendnet,tew-823dru)
 		ucidef_add_switch "switch0" \
-			"0@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6@eth0"
+			"0u@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6u@eth0"
 		;;
 	buffalo,wzr-450hp2)
 		ucidef_add_switch "switch0" \
-			"6@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0@eth0"
+			"6u@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0u@eth0"
 		;;
 	buffalo,wzr-600dhp|\
 	buffalo,wzr-hp-ag300h|\
@@ -287,7 +287,7 @@ ath79_setup_interfaces()
 	comfast,cf-wr650ac-v2|\
 	zyxel,nbg6616)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6@eth1"
+			"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6u@eth1"
 		;;
 	compex,wpj344-16m|\
 	compex,wpj563)
@@ -301,7 +301,7 @@ ath79_setup_interfaces()
 	dell,apl26-0ae|\
 	dell,apl27-0b1)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "2:lan:1" "3:lan:2" "6@eth1"
+			"0u@eth0" "2:lan:1" "3:lan:2" "6u@eth1"
 		;;
 	devolo,dlan-pro-1200plus-ac|\
 	devolo,magic-2-wifi)
@@ -318,11 +318,11 @@ ath79_setup_interfaces()
 		;;
 	dlink,dap-2695-a1)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "2:lan" "3:wan" "6@eth1"
+			"0u@eth0" "2:lan" "3:wan" "6u@eth1"
 		;;
 	dlink,dap-3662-a1)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "1:lan:2" "2:lan:1" "6@eth1"
+			"0u@eth0" "1:lan:2" "2:lan:1" "6u@eth1"
 		;;
 	dlink,dch-g020-a1)
 		ucidef_add_switch "switch0" \
@@ -393,7 +393,7 @@ ath79_setup_interfaces()
 		;;
 	jjplus,jwap230)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "5:wan:1" "1:lan:2" "6@eth1"
+			"0u@eth0" "5:wan:1" "1:lan:2" "6u@eth1"
 		;;
 	joyit,jt-or750i)
 		ucidef_set_interface_wan "eth1"
@@ -416,7 +416,7 @@ ath79_setup_interfaces()
 		;;
 	librerouter,librerouter-v1)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "5:wan" "6@eth1" "4:lan"
+			"0u@eth0" "5:wan" "6u@eth1" "4:lan"
 		;;
 	longdata,aps256)
 		ucidef_set_interface_wan "eth1"
@@ -512,7 +512,7 @@ ath79_setup_interfaces()
 		;;
 	ruckus,r500)
 		ucidef_add_switch "switch0" \
-			"6u@eth0" "5:lan:1" "3:lan:2" "0@eth1"
+			"6u@eth0" "5:lan:1" "3:lan:2" "0u@eth1"
 		;;
 	teltonika,rut955|\
 	teltonika,rut955-h7v3c0)
@@ -527,7 +527,7 @@ ath79_setup_interfaces()
 	tplink,archer-d7-v1|\
 	tplink,archer-d7b-v1)
 		ucidef_add_switch "switch0" \
-			"0@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6@eth0" "2:wan:4" "1:wan:5"
+			"0u@eth1" "3:lan:3" "4:lan:2" "5:lan:1" "6u@eth0" "2:wan:4" "1:wan:5"
 		;;
 	tplink,deco-m4r-v1|\
 	tplink,deco-s4-v2)
@@ -567,7 +567,7 @@ ath79_setup_interfaces()
 	tplink,tl-wr1043nd-v3|\
 	tplink,tl-wr1045nd-v2)
 		ucidef_add_switch "switch0" \
-			"0@eth1" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan" "6@eth0"
+			"0u@eth1" "1:lan:4" "2:lan:3" "3:lan:2" "4:lan:1" "5:wan" "6u@eth0"
 		;;
 	tplink,tl-wr2543-v1)
 		ucidef_add_switch "switch0" \

target/linux/ath79/generic/base-files/etc/board.d/02_network

@@ -13,7 +13,7 @@ ath79_setup_interfaces()
 		;;
 	domywifi,dw33d)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "1:wan" "2:lan" "3:lan" "4:lan" "5:lan" "6@eth1"
+			"0u@eth0" "1:wan" "2:lan" "3:lan" "4:lan" "5:lan" "6u@eth1"
 		;;
 	dongwon,dw02-412h-64m|\
 	dongwon,dw02-412h-128m)
@@ -42,7 +42,7 @@ ath79_setup_interfaces()
 		;;
 	linksys,ea4500-v3)
 		ucidef_add_switch "switch0" \
-			"6@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0@eth0"
+			"6u@eth1" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "0u@eth0"
 		;;
 	netgear,pgzng1)
 		ucidef_set_interfaces_lan_wan "eth1" "eth0"
@@ -81,7 +81,7 @@ ath79_setup_interfaces()
 	zyxel,emg2926-q10a|\
 	zyxel,nbg6716)
 		ucidef_add_switch "switch0" \
-			"0@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6@eth1"
+			"0u@eth0" "1:lan" "2:lan" "3:lan" "4:lan" "5:wan" "6u@eth1"
 		;;
 	*)
 		ucidef_set_interfaces_lan_wan "eth0" "eth1"

target/linux/ath79/nand/base-files/etc/board.d/02_network

@@ -7,13 +7,14 @@ menuconfig COMMON_CLK_REALTEK
 if COMMON_CLK_REALTEK
 
 config COMMON_CLK_RTL83XX
-	bool "Clock driver for Realtek RTL83XX"
+	bool "Clock driver for Realtek RTL83XX and RTL960X"
 	depends on MACH_REALTEK_RTL
 	select SRAM
 	help
 	  This driver adds support for the Realtek RTL83xx series basic clocks.
 	  This includes chips in the RTL838x series, such as RTL8380, RTL8381,
-	  RTL832, as well as chips from the RTL839x series, such as RTL8390,
-	  RT8391, RTL8392, RTL8393 and RTL8396.
+	  RTL832, chips from the RTL839x series, such as RTL8390, RT8391,
+	  RTL8392, RTL8393 and RTL8396 as well as chips from the RTL960X
+	  series, such as RTL9607C, RTL8198D.
 
 endif

target/linux/realtek/files-6.12/drivers/clk/realtek/Kconfig

@@ -92,7 +92,8 @@
 
 #define SOC_RTL838X		0
 #define SOC_RTL839X		1
-#define SOC_COUNT		2
+#define SOC_RTL960X		2
+#define SOC_COUNT		3
 
 #define MEM_DDR1		1
 #define MEM_DDR2		2
@@ -264,6 +265,8 @@ static const struct rtcl_round_set rtcl_round_set[SOC_COUNT][CLK_COUNT] = {
 		RTCL_ROUND_SET(400000000, 850000000, 25000000),
 		RTCL_ROUND_SET(100000000, 400000000, 25000000),
 		RTCL_ROUND_SET(50000000, 200000000, 50000000)
+	}, {
+		RTCL_ROUND_SET(500000000, 1200000000, 25000000)
 	}
 };
 
@@ -465,6 +468,91 @@ static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long
 	return rrate;
 }
 
+static unsigned long rtcl_960x_cpu_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 ocp_pll_ctrl0, ocp_pll_ctrl3, cmu_gcr;
+	u32 cpu_freq_sel0, en_div2_cpu0, cmu_mode, freq_div;
+	unsigned long rate;
+
+	ocp_pll_ctrl0 = read_soc(RTL960X_OCP_PLL_CTRL0);
+	ocp_pll_ctrl3 = read_soc(RTL960X_OCP_PLL_CTRL3);
+	cmu_gcr = read_soc(RTL960X_CMU_GCR);
+
+	cpu_freq_sel0 = RTL960X_OCP_CTRL0_CPU_FREQ_SEL0(ocp_pll_ctrl0);
+	en_div2_cpu0 = RTL960X_OCP_CTRL3_EN_DIV2_CPU0(ocp_pll_ctrl3);
+	cmu_mode = RTL960X_CMU_GCR_CMU_MODE(cmu_gcr);
+	freq_div = RTL960X_CMU_GCR_FREQ_DIV(cmu_gcr);
+
+	rate = ((cpu_freq_sel0 + 2) * 2 * parent_rate) >> en_div2_cpu0;
+	if (cmu_mode != 0)
+		rate >>= freq_div;
+
+	return rate;
+}
+
+static unsigned long rtcl_960x_lxb_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 phy_rg5x_pll, lx_freq_sel;
+	unsigned long rate;
+
+	phy_rg5x_pll = read_sw(RTL960X_PHY_RG5X_PLL);
+	lx_freq_sel = RTL960X_LX_FREQ_SEL(phy_rg5x_pll);
+
+	rate = (40 * parent_rate) / (lx_freq_sel + 5);
+
+	return rate;
+}
+
+static unsigned long rtcl_960x_mem_recalc_rate(struct clk_hw *hw,
+					     unsigned long parent_rate)
+{
+	u32 mem_pll_ctrl2, mem_pll_ctrl3, mem_pll_ctrl5;
+	u32 n_code, pdiv, f_code;
+	unsigned long rate;
+	u64 t;
+
+	mem_pll_ctrl2 = read_soc(RTL960X_MEM_PLL_CTRL2);
+	mem_pll_ctrl3 = read_soc(RTL960X_MEM_PLL_CTRL3);
+	mem_pll_ctrl5 = read_soc(RTL960X_MEM_PLL_CTRL5);
+
+	pdiv = RTL960X_MEM_CTRL2_PDIV(mem_pll_ctrl2);
+	n_code = RTL960X_MEM_CTRL3_N_CODE(mem_pll_ctrl3);
+	f_code = RTL960X_MEM_CTRL5_F_CODE(mem_pll_ctrl5);
+
+	rate = (parent_rate * (n_code + 3)) / (2 * (1 << pdiv));
+	t = parent_rate;
+	t *= f_code;
+	t /= 16384;
+	rate += t;
+
+	return rate;
+}
+
+static unsigned long rtcl_960x_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct rtcl_clk *clk = rtcl_hw_to_clk(hw);
+	unsigned long rate;
+
+	if ((clk->idx >= CLK_COUNT) || (!rtcl_ccu) || (rtcl_ccu->soc >= SOC_COUNT))
+		return 0;
+
+	switch (clk->idx) {
+	case CLK_CPU:
+		rate = rtcl_960x_cpu_recalc_rate(hw, parent_rate);
+		break;
+	case CLK_MEM:
+		rate = rtcl_960x_mem_recalc_rate(hw, parent_rate);
+		break;
+	case CLK_LXB:
+		rate = rtcl_960x_lxb_recalc_rate(hw, parent_rate);
+		break;
+	}
+
+	return rate;
+}
+
 /*
  * Initialization functions to register the CCU and its clocks
  */
@@ -474,6 +562,10 @@ static long rtcl_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long
 				  (void *)&rtcl_##SOC##_dram_start) +	\
 				  (void *)PBASE; })
 
+static const struct clk_ops rtcl_960x_clk_ops = {
+	.recalc_rate = rtcl_960x_recalc_rate,
+};
+
 static const struct clk_ops rtcl_clk_ops = {
 	.set_rate = rtcl_set_rate,
 	.round_rate = rtcl_round_rate,
@@ -488,6 +580,8 @@ static int rtcl_ccu_create(struct device_node *np)
 		soc = SOC_RTL838X;
 	else if (of_device_is_compatible(np, "realtek,rtl8390-clock"))
 		soc = SOC_RTL839X;
+	else if (of_device_is_compatible(np, "realtek,rtl9607-clock"))
+		soc = SOC_RTL960X;
 	else
 		return -ENXIO;
 
@@ -516,10 +610,14 @@ static int rtcl_register_clkhw(int clk_idx)
 	rclk->hw.init = &hw_init;
 
 	hw_init.num_parents = 1;
-	hw_init.ops = &rtcl_clk_ops;
 	hw_init.parent_data = &parent_data;
 	hw_init.name = rtcl_clk_info[clk_idx].name;
 
+	if (rtcl_ccu->soc == SOC_RTL960X)
+		hw_init.ops = &rtcl_960x_clk_ops;
+	else
+		hw_init.ops = &rtcl_clk_ops;
+
 	ret = of_clk_hw_register(rtcl_ccu->np, &rclk->hw);
 	if (ret)
 		return ret;
@@ -719,6 +817,7 @@ static void __init rtcl_probe_early(struct device_node *np)
 
 CLK_OF_DECLARE_DRIVER(rtl838x_clk, "realtek,rtl8380-clock", rtcl_probe_early);
 CLK_OF_DECLARE_DRIVER(rtl839x_clk, "realtek,rtl8390-clock", rtcl_probe_early);
+CLK_OF_DECLARE_DRIVER(rtl960x_clk, "realtek,rtl9607-clock", rtcl_probe_early);
 
 /*
  * Late registration: Finally register as normal platform driver. At this point