Skip to content

Commit 01bb639

Browse files
toppercsmallp-o-p
topperc
authored and
smallp-o-p
committed
[RISCV] Remove duplicate vector conversion pseudos. (llvm#114287)
These pseudos used to be handled by CustomInserter to insert the rounding mode change for vector ceil, floor, etc. At some point they were changed to use the InsertReadWriteCSR pass instead of the custom inserter. I believe that makes them redundant with the pseudos used by the RVV intrinsics with rounding mode operand.
1 parent 714ae91 commit 01bb639

File tree

2 files changed

+10
-124
lines changed

2 files changed

+10
-124
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -1134,46 +1134,6 @@ class VPseudoUnaryMask_NoExcept<VReg RetClass,
11341134
let usesCustomInserter = 1;
11351135
}
11361136

1137-
class VPseudoUnaryNoMask_FRM<VReg RetClass,
1138-
VReg OpClass,
1139-
string Constraint = "",
1140-
bits<2> TargetConstraintType = 1> :
1141-
Pseudo<(outs RetClass:$rd),
1142-
(ins RetClass:$passthru, OpClass:$rs2, vec_rm:$frm,
1143-
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1144-
RISCVVPseudo {
1145-
let mayLoad = 0;
1146-
let mayStore = 0;
1147-
let hasSideEffects = 0;
1148-
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
1149-
let TargetOverlapConstraintType = TargetConstraintType;
1150-
let HasVLOp = 1;
1151-
let HasSEWOp = 1;
1152-
let HasVecPolicyOp = 1;
1153-
let HasRoundModeOp = 1;
1154-
}
1155-
1156-
class VPseudoUnaryMask_FRM<VReg RetClass,
1157-
VReg OpClass,
1158-
string Constraint = "",
1159-
bits<2> TargetConstraintType = 1> :
1160-
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
1161-
(ins GetVRegNoV0<RetClass>.R:$passthru, OpClass:$rs2,
1162-
VMaskOp:$vm, vec_rm:$frm,
1163-
AVL:$vl, sew:$sew, vec_policy:$policy), []>,
1164-
RISCVVPseudo {
1165-
let mayLoad = 0;
1166-
let mayStore = 0;
1167-
let hasSideEffects = 0;
1168-
let Constraints = !interleave([Constraint, "$rd = $passthru"], ",");
1169-
let TargetOverlapConstraintType = TargetConstraintType;
1170-
let HasVLOp = 1;
1171-
let HasSEWOp = 1;
1172-
let HasVecPolicyOp = 1;
1173-
let UsesMaskPolicy = 1;
1174-
let HasRoundModeOp = 1;
1175-
}
1176-
11771137
class VPseudoUnaryNoMaskGPROut :
11781138
Pseudo<(outs GPR:$rd),
11791139
(ins VR:$rs2, AVL:$vl, sew:$sew), []>,
@@ -3578,23 +3538,6 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
35783538
}
35793539
}
35803540

3581-
3582-
multiclass VPseudoConversionRM<VReg RetClass,
3583-
VReg Op1Class,
3584-
LMULInfo MInfo,
3585-
string Constraint = "",
3586-
int sew = 0,
3587-
bits<2> TargetConstraintType = 1> {
3588-
let VLMul = MInfo.value, SEW=sew in {
3589-
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
3590-
def suffix : VPseudoUnaryNoMask_FRM<RetClass, Op1Class,
3591-
Constraint, TargetConstraintType>;
3592-
def suffix # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
3593-
Constraint, TargetConstraintType>,
3594-
RISCVMaskedPseudo<MaskIdx=2>;
3595-
}
3596-
}
3597-
35983541
multiclass VPseudoConversionNoExcept<VReg RetClass,
35993542
VReg Op1Class,
36003543
LMULInfo MInfo,
@@ -3620,14 +3563,6 @@ multiclass VPseudoVCVTI_V_RM {
36203563
}
36213564
}
36223565

3623-
multiclass VPseudoVCVTI_RM_V {
3624-
foreach m = MxListF in {
3625-
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
3626-
SchedUnary<"WriteVFCvtFToIV", "ReadVFCvtFToIV", m.MX,
3627-
forcePassthruRead=true>;
3628-
}
3629-
}
3630-
36313566
multiclass VPseudoVFROUND_NOEXCEPT_V {
36323567
foreach m = MxListF in {
36333568
defm _V : VPseudoConversionNoExcept<m.vrclass, m.vrclass, m>,
@@ -3645,15 +3580,6 @@ multiclass VPseudoVCVTF_V_RM {
36453580
}
36463581
}
36473582

3648-
multiclass VPseudoVCVTF_RM_V {
3649-
foreach m = MxListF in {
3650-
foreach e = SchedSEWSet<m.MX, isF=1>.val in
3651-
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m, sew=e>,
3652-
SchedUnary<"WriteVFCvtIToFV", "ReadVFCvtIToFV", m.MX, e,
3653-
forcePassthruRead=true>;
3654-
}
3655-
}
3656-
36573583
multiclass VPseudoVWCVTI_V {
36583584
defvar constraint = "@earlyclobber $rd";
36593585
foreach m = MxListFW in {
@@ -3672,15 +3598,6 @@ multiclass VPseudoVWCVTI_V_RM {
36723598
}
36733599
}
36743600

3675-
multiclass VPseudoVWCVTI_RM_V {
3676-
defvar constraint = "@earlyclobber $rd";
3677-
foreach m = MxListFW in {
3678-
defm _V : VPseudoConversionRM<m.wvrclass, m.vrclass, m, constraint>,
3679-
SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
3680-
forcePassthruRead=true>;
3681-
}
3682-
}
3683-
36843601
multiclass VPseudoVWCVTF_V {
36853602
defvar constraint = "@earlyclobber $rd";
36863603
foreach m = MxListW in {
@@ -3721,15 +3638,6 @@ multiclass VPseudoVNCVTI_W_RM {
37213638
}
37223639
}
37233640

3724-
multiclass VPseudoVNCVTI_RM_W {
3725-
defvar constraint = "@earlyclobber $rd";
3726-
foreach m = MxListW in {
3727-
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
3728-
SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
3729-
forcePassthruRead=true>;
3730-
}
3731-
}
3732-
37333641
multiclass VPseudoVNCVTF_W_RM {
37343642
defvar constraint = "@earlyclobber $rd";
37353643
foreach m = MxListFW in {
@@ -3742,17 +3650,6 @@ multiclass VPseudoVNCVTF_W_RM {
37423650
}
37433651
}
37443652

3745-
multiclass VPseudoVNCVTF_RM_W {
3746-
defvar constraint = "@earlyclobber $rd";
3747-
foreach m = MxListFW in {
3748-
foreach e = SchedSEWSet<m.MX, isF=1, isWidening=1>.val in
3749-
defm _W : VPseudoConversionRM<m.vrclass, m.wvrclass, m, constraint, sew=e,
3750-
TargetConstraintType=2>,
3751-
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX, e,
3752-
forcePassthruRead=true>;
3753-
}
3754-
}
3755-
37563653
multiclass VPseudoVNCVTD_W {
37573654
defvar constraint = "@earlyclobber $rd";
37583655
foreach m = MxListFW in {
@@ -6583,9 +6480,6 @@ defm PseudoVFCVT_XU_F : VPseudoVCVTI_V_RM;
65836480
defm PseudoVFCVT_X_F : VPseudoVCVTI_V_RM;
65846481
}
65856482

6586-
defm PseudoVFCVT_RM_XU_F : VPseudoVCVTI_RM_V;
6587-
defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V;
6588-
65896483
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
65906484
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
65916485

@@ -6594,8 +6488,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
65946488
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V_RM;
65956489
defm PseudoVFCVT_F_X : VPseudoVCVTF_V_RM;
65966490
}
6597-
defm PseudoVFCVT_RM_F_XU : VPseudoVCVTF_RM_V;
6598-
defm PseudoVFCVT_RM_F_X : VPseudoVCVTF_RM_V;
65996491
} // mayRaiseFPException = true
66006492

66016493
//===----------------------------------------------------------------------===//
@@ -6606,8 +6498,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66066498
defm PseudoVFWCVT_XU_F : VPseudoVWCVTI_V_RM;
66076499
defm PseudoVFWCVT_X_F : VPseudoVWCVTI_V_RM;
66086500
}
6609-
defm PseudoVFWCVT_RM_XU_F : VPseudoVWCVTI_RM_V;
6610-
defm PseudoVFWCVT_RM_X_F : VPseudoVWCVTI_RM_V;
66116501

66126502
defm PseudoVFWCVT_RTZ_XU_F : VPseudoVWCVTI_V;
66136503
defm PseudoVFWCVT_RTZ_X_F : VPseudoVWCVTI_V;
@@ -6627,8 +6517,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66276517
defm PseudoVFNCVT_XU_F : VPseudoVNCVTI_W_RM;
66286518
defm PseudoVFNCVT_X_F : VPseudoVNCVTI_W_RM;
66296519
}
6630-
defm PseudoVFNCVT_RM_XU_F : VPseudoVNCVTI_RM_W;
6631-
defm PseudoVFNCVT_RM_X_F : VPseudoVNCVTI_RM_W;
66326520

66336521
defm PseudoVFNCVT_RTZ_XU_F : VPseudoVNCVTI_W;
66346522
defm PseudoVFNCVT_RTZ_X_F : VPseudoVNCVTI_W;
@@ -6637,8 +6525,6 @@ let hasSideEffects = 0, hasPostISelHook = 1 in {
66376525
defm PseudoVFNCVT_F_XU : VPseudoVNCVTF_W_RM;
66386526
defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM;
66396527
}
6640-
defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W;
6641-
defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W;
66426528

66436529
let hasSideEffects = 0, hasPostISelHook = 1 in {
66446530
defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM;

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2639,23 +2639,23 @@ foreach fvti = AllFloatVectors in {
26392639
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
26402640
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFCVT_XU_F_V">;
26412641
defm : VPatConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFCVT_X_F_V">;
2642-
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_RM_XU_F_V">;
2643-
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
2642+
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFCVT_XU_F_V">;
2643+
defm : VPatConvertFP2I_RM_VL_V<any_riscv_vfcvt_rm_x_f_vl, "PseudoVFCVT_X_F_V">;
26442644

26452645
defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFCVT_RTZ_XU_F_V">;
26462646
defm : VPatConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFCVT_RTZ_X_F_V">;
26472647

26482648
defm : VPatConvertI2FPVL_V_RM<any_riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
26492649
defm : VPatConvertI2FPVL_V_RM<any_riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
26502650

2651-
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_RM_F_XU_V">;
2652-
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_RM_F_X_V">;
2651+
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_xu_vl, "PseudoVFCVT_F_XU_V">;
2652+
defm : VPatConvertI2FP_RM_VL_V<riscv_vfcvt_rm_f_x_vl, "PseudoVFCVT_F_X_V">;
26532653

26542654
// 13.18. Widening Floating-Point/Integer Type-Convert Instructions
26552655
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
26562656
defm : VPatWConvertFP2IVL_V_RM<riscv_vfcvt_x_f_vl, "PseudoVFWCVT_X_F_V">;
2657-
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_RM_XU_F_V">;
2658-
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_RM_X_F_V">;
2657+
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_xu_f_vl, "PseudoVFWCVT_XU_F_V">;
2658+
defm : VPatWConvertFP2I_RM_VL_V<riscv_vfcvt_rm_x_f_vl, "PseudoVFWCVT_X_F_V">;
26592659

26602660
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
26612661
defm : VPatWConvertFP2IVL_V<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFWCVT_RTZ_X_F_V">;
@@ -2696,17 +2696,17 @@ foreach fvtiToFWti = AllWidenableBFloatToFloatVectors in {
26962696
// 13.19 Narrowing Floating-Point/Integer Type-Convert Instructions
26972697
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
26982698
defm : VPatNConvertFP2IVL_W_RM<riscv_vfcvt_x_f_vl, "PseudoVFNCVT_X_F_W">;
2699-
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_RM_XU_F_W">;
2700-
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_RM_X_F_W">;
2699+
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_xu_f_vl, "PseudoVFNCVT_XU_F_W">;
2700+
defm : VPatNConvertFP2I_RM_VL_W<riscv_vfcvt_rm_x_f_vl, "PseudoVFNCVT_X_F_W">;
27012701

27022702
defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_xu_f_vl, "PseudoVFNCVT_RTZ_XU_F_W">;
27032703
defm : VPatNConvertFP2IVL_W<any_riscv_vfcvt_rtz_x_f_vl, "PseudoVFNCVT_RTZ_X_F_W">;
27042704

27052705
defm : VPatNConvertI2FPVL_W_RM<any_riscv_uint_to_fp_vl, "PseudoVFNCVT_F_XU_W">;
27062706
defm : VPatNConvertI2FPVL_W_RM<any_riscv_sint_to_fp_vl, "PseudoVFNCVT_F_X_W">;
27072707

2708-
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_RM_F_XU_W">;
2709-
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_RM_F_X_W">;
2708+
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_xu_vl, "PseudoVFNCVT_F_XU_W">;
2709+
defm : VPatNConvertI2FP_RM_VL_W<riscv_vfcvt_rm_f_x_vl, "PseudoVFNCVT_F_X_W">;
27102710

27112711
foreach fvtiToFWti = AllWidenableFloatVectors in {
27122712
defvar fvti = fvtiToFWti.Vti;

0 commit comments

Comments
 (0)