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Implement review items
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-6
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3 files changed

+20
-6
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Cargo.toml

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@@ -20,4 +20,6 @@ embedded-hal = "1.0.0"
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[features]
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mosi_idle_high = []
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# Send the reset command in one single transaction
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reset_single_transaction = []
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std = []

README.md

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@@ -39,7 +39,7 @@ It provides three variants:
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It may also be a timing issue with the first bit being sent, this is the case
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on the stm32f030 with 2MHz.
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You could try using the `mosi_idle_high` feature, it might help.
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You could try using the `mosi_idle_high` and `reset_single_transaction` features, they might help.
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If this does not help you can try different `embedded_hal::spi::Mode` parameters. For example on
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stm32f411 (as used for example on the Black Pill board) you have to set `phase` to

src/prerendered.rs

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@@ -11,6 +11,8 @@ use core::marker::PhantomData;
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use smart_leds_trait::{SmartLedsWrite, RGB8, RGBW};
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const FLUSH_DATA_LEN: usize = 140;
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/// SPI mode that can be used for this crate
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///
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/// Provided for convenience
@@ -114,18 +116,28 @@ where
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}
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/// Add a reset sequence (140 zeroes) to the data buffer
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#[cfg(feature = "reset_single_transaction")]
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fn flush(&mut self) -> Result<(), Error<E>> {
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const FLUSH_DATA_LEN: usize = 140;
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const FLUSH_DATA: &[u8] = &[0x00; FLUSH_DATA_LEN];
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let flush_data = [(); FLUSH_DATA_LEN].map(|_| 0);
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if self.index + FLUSH_DATA_LEN > self.data.len() {
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return Err(Error::OutOfBounds);
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}
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self.data[self.index..(self.index + FLUSH_DATA_LEN)].copy_from_slice(FLUSH_DATA);
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self.data[self.index..(self.index + FLUSH_DATA_LEN)].copy_from_slice(&flush_data);
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self.index += FLUSH_DATA_LEN;
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Ok(())
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}
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/// Send a reset sequence (140 zeroes) on the bus
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#[cfg(not(feature = "reset_single_transaction"))]
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fn flush(&mut self) -> Result<(), Error<E>> {
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for _ in 0..FLUSH_DATA_LEN {
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self.spi.write(&[0]).map_err(Error::Spi)?;
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}
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Ok(())
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}
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fn send_data(&mut self) -> Result<(), E> {
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self.spi.write(&self.data[..self.index])
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}
@@ -157,7 +169,7 @@ where
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}
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self.flush()?;
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self.send_data().map_err(|e| Error::Spi(e))
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self.send_data().map_err(Error::Spi)
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}
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}
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@@ -188,6 +200,6 @@ where
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}
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self.flush()?;
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self.send_data().map_err(|e| Error::Spi(e))
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self.send_data().map_err(Error::Spi)
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}
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}

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