Documentation: PR#3501 improvements suggested by BsAtHome

Author: smoe

docs/src/man/man9/hm2_rpspi.9.adoc

@@ -97,28 +97,33 @@ TBD.
 == SPI CLOCK RATES
 
 The maximum SPI clock of the BCM2835-SPI driver and the 7i90 is
-documented over 32MHz. The SPI driver can provide frequencies well
+documented over 32␗MHz. The SPI driver can provide frequencies well
 beyond what is acceptable for the 7i90. A safe value to start with would
-be 12.5 MHz (spiclk_rate=12500) and then work your way up from there.
+be 12.5 MHz (spiclk_rate=12500) and then work your way up from there.
 
 The SPI driver generates (very) discrete clock frequency values,
 especially in the MHz range because of a simple clock divider structure.
-The base frequency is 250 MHz and the divider for SPI0/SPI1 scales using
+The base frequency is 250 MHz and the divider for SPI0/SPI1 scales using
 discrete factors. The following list specifies the *spiclk_rate* setting
-and the discrete SPI clock frequency (250 MHz / (2n) for n > 1):
-- 62500 - 62.500 MHz,
-- 41667 - 41.667 MHz,
-- 31250 - 31.250 MHz,
-- 25000 - 25.000 MHz,
-- 20834 - 20.833 MHz,
-- 17858 - 17.857 MHz,
-- 15625 - 15.625 MHz,
-- 13889 - 13.889 MHz,
-- 12500 - 12.500 MHz,
-- 11364 - 11.364 MHz,
-- 10417 - 10.417 MHz,
-- 9616 - 9.615 MHz,
-- ....
+and the discrete SPI clock frequency (250 MHz / (2__n__) for _n_ > 1):
+
+[cols=">,>"]
+|===
+| _n_ | Frequency range             |
+|   2 | 62500 - 62.500 MHz, |
+|   3 | 41667 - 41.667 MHz, |
+|   4 | 31250 - 31.250 MHz, |
+|   5 | 25000 - 25.000 MHz, |
+|   6 | 20834 - 20.833 MHz, |
+|   7 | 17858 - 17.857 MHz, |
+|   8 | 15625 - 15.625 MHz, |
+|   9 | 13889 - 13.889 MHz, |
+|  10 | 12500 - 12.500 MHz, |
+|  11 | 11364 - 11.364 MHz, |
+|  12 | 10417 - 10.417 MHz, |
+|  13 |  9616 -  9.615 MHz, |
+| 14+ | ....                      |
+|===
 
 The lowest selectable SPI clock frequency is 30 kHz (spiclk_rate=30) for
 SPI0 and SPI1. Theoretically, the SPI0 port could go slower, but there
@@ -138,8 +143,8 @@ Writing to the 7i90 may be done faster than reading. This is especially
 important if you have "long" wires or any buffers on the SPI-bus path.
 You can set the read clock frequency to a lower value (using
 *spiclk_rate_rd*) to counter the effects of the SPI-bus round-trip
-needed for read actions. For example, you can write at 41.67 MHz and
-read at 25.00 MHz.
+needed for read actions. For example, you can write at 41.67␗MHz and
+read at 25.00␗MHz.
 
 It should be noted that the Rpi3 *must* have an adequate 5V power supply
 and the power should be properly decoupled right on the 40-pin I/O