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[X86] Fixes for AMD znver5 enablement (llvm#159237)
- cpuid bit for prefetchi is different from Intel (https://docs.amd.com/v/u/en-US/24594_3.37) - Fix cpu family model numbers
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2 files changed

+15
-3
lines changed
  • compiler-rt/lib/builtins/cpu_model
  • llvm/lib/TargetParser

2 files changed

+15
-3
lines changed

compiler-rt/lib/builtins/cpu_model/x86.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1094,6 +1094,12 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
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if (HasExtLeaf8 && ((EBX >> 9) & 1))
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setFeature(FEATURE_WBNOINVD);
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1097+
bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&
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!getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);
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// AMD cpuid bit for prefetchi is different from Intel
1100+
if (HasExtLeaf21 && ((EAX >> 20) & 1))
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setFeature(FEATURE_PREFETCHI);
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bool HasLeaf14 = MaxLevel >= 0x14 &&
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!getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
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if (HasLeaf14 && ((EBX >> 4) & 1))

llvm/lib/TargetParser/Host.cpp

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1302,16 +1302,17 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
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case 26:
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CPU = "znver5";
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*Type = X86::AMDFAM1AH;
1305-
if (Model <= 0x77) {
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if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) ||
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(Model >= 0xd0 && Model <= 0xd7)) {
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// Models 00h-0Fh (Breithorn).
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// Models 10h-1Fh (Breithorn-Dense).
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// Models 20h-2Fh (Strix 1).
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// Models 30h-37h (Strix 2).
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// Models 38h-3Fh (Strix 3).
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// Models 40h-4Fh (Granite Ridge).
1312-
// Models 50h-5Fh (Weisshorn).
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// Models 60h-6Fh (Krackan1).
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// Models 70h-77h (Sarlak).
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// Models D0h-D7h (Annapurna).
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CPU = "znver5";
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*Subtype = X86::AMDFAM1AH_ZNVER5;
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break; // "znver5"
@@ -2049,6 +2050,11 @@ StringMap<bool> sys::getHostCPUFeatures() {
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Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
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Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);
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2053+
bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&
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!getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);
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// AMD cpuid bit for prefetchi is different from Intel
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Features["prefetchi"] = HasExtLeaf21 && ((EAX >> 20) & 1);
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bool HasLeaf7 =
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MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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@@ -2131,7 +2137,7 @@ StringMap<bool> sys::getHostCPUFeatures() {
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Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
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Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
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Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
2134-
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
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Features["prefetchi"] |= HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
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Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
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bool HasAVX10 = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
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bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);

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