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Conversion/Project1/Project1

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Reference, Quantity, Value, Footprint, Datasheet, PROD_ID
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P1 P2 ,2,CONN_01X02,Pin_Headers:Pin_Header_Straight_1x02,
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U1 ,1,4069,SMD_Packages:SOIC-14_N,,STN-00666
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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# 4069
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#
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DEF 4069 U 0 30 Y Y 6 F N
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F0 "U" 195 115 50 H V C CNN
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F1 "4069" 190 -125 50 H V C CNN
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F2 "" 0 0 60 H I C CNN
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F3 "" 0 0 60 H I C CNN
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DRAW
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P 4 0 0 0 -150 150 -150 -150 150 0 -150 150 N
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X VSS 7 -50 -100 0 U 40 40 0 0 W N
14+
X VDD 14 -50 100 0 U 40 40 0 0 W N
15+
X ~ 1 -450 0 300 R 50 50 1 1 I
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X ~ 2 450 0 300 L 50 50 1 1 O I
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X ~ 3 -450 0 300 R 50 50 2 1 I
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X ~ 4 450 0 300 L 50 50 2 1 O I
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X ~ 5 -450 0 300 R 50 50 3 1 I
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X ~ 6 450 0 300 L 50 50 3 1 O I
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X ~ 8 450 0 300 L 50 50 4 1 O I
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X ~ 9 -450 0 300 R 50 50 4 1 I
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X ~ 10 450 0 300 L 50 50 5 1 O I
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X ~ 11 -450 0 300 R 50 50 5 1 I
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X ~ 12 450 0 300 L 50 50 6 1 O I
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X ~ 13 -450 0 300 R 50 50 6 1 I
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X ~ 1 -450 0 300 R 50 50 1 2 I I
28+
X ~ 2 450 0 300 L 50 50 1 2 O
29+
X ~ 3 -450 0 300 R 50 50 2 2 I I
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X ~ 4 450 0 300 L 50 50 2 2 O
31+
X ~ 5 -450 0 300 R 50 50 3 2 I I
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X ~ 6 450 0 300 L 50 50 3 2 O
33+
X ~ 8 450 0 300 L 50 50 4 2 O
34+
X ~ 9 -450 0 300 R 50 50 4 2 I I
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X ~ 10 450 0 300 L 50 50 5 2 O
36+
X ~ 11 -450 0 300 R 50 50 5 2 I I
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X ~ 12 450 0 300 L 50 50 6 2 O
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X ~ 13 -450 0 300 R 50 50 6 2 I I
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ENDDRAW
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ENDDEF
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#
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# CONN_01X02
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#
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DEF CONN_01X02 P 0 40 Y N 1 F N
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F0 "P" 0 150 50 H V C CNN
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F1 "CONN_01X02" 100 0 50 V V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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$FPLIST
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Pin_Header_Straight_1X02
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Pin_Header_Angled_1X02
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Socket_Strip_Straight_1X02
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Socket_Strip_Angled_1X02
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$ENDFPLIST
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DRAW
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S -50 -45 10 -55 0 1 0 N
57+
S -50 55 10 45 0 1 0 N
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S -50 100 50 -100 0 1 0 N
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X P1 1 -200 50 150 R 50 50 1 1 P
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X P2 2 -200 -50 150 R 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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#End Library

Conversion/Project1/Project1.bak

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EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:microcontrollers
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LIBS:dsp
15+
LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
24+
LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:Project1-cache
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EELAYER 25 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
36+
Sheet 1 1
37+
Title ""
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Date ""
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Rev ""
40+
Comp ""
41+
Comment1 ""
42+
Comment2 ""
43+
Comment3 ""
44+
Comment4 ""
45+
$EndDescr
46+
$Comp
47+
L CONN_01X02 P2
48+
U 1 1 5886C74A
49+
P 2450 2950
50+
F 0 "P2" H 2450 3100 50 0000 C CNN
51+
F 1 "CONN_01X02" V 2550 2950 50 0000 C CNN
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F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 2450 2950 50 0001 C CNN
53+
F 3 "" H 2450 2950 50 0000 C CNN
54+
1 2450 2950
55+
1 0 0 -1
56+
$EndComp
57+
$Comp
58+
L CONN_01X02 P1
59+
U 1 1 5886C7CF
60+
P 4750 2000
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F 0 "P1" H 4750 2150 50 0000 C CNN
62+
F 1 "CONN_01X02" V 4850 2000 50 0000 C CNN
63+
F 2 "Pin_Headers:Pin_Header_Straight_1x02" H 4750 2000 50 0001 C CNN
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F 3 "" H 4750 2000 50 0000 C CNN
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1 4750 2000
66+
0 -1 -1 0
67+
$EndComp
68+
$Comp
69+
L 4069 U1
70+
U 1 1 5886C840
71+
P 3850 2950
72+
F 0 "U1" H 4045 3065 50 0000 C CNN
73+
F 1 "4069" H 4040 2825 50 0000 C CNN
74+
F 2 "SMD_Packages:SO-16-N" H 3850 2950 60 0001 C CNN
75+
F 3 "" H 3850 2950 60 0001 C CNN
76+
1 3850 2950
77+
1 0 0 -1
78+
$EndComp
79+
Wire Wire Line
80+
3400 2950 3400 3200
81+
Wire Wire Line
82+
3400 3200 4800 3200
83+
Wire Wire Line
84+
4800 3200 4800 2200
85+
Wire Wire Line
86+
4700 2200 4700 2950
87+
Wire Wire Line
88+
4700 2950 4300 2950
89+
Wire Wire Line
90+
2250 2900 2050 2900
91+
Wire Wire Line
92+
2050 2900 2050 2600
93+
Wire Wire Line
94+
2250 3000 2050 3000
95+
Wire Wire Line
96+
2050 3000 2050 3250
97+
Text GLabel 2050 2600 0 60 Input ~ 0
98+
VDD
99+
Text GLabel 2050 3250 0 60 Input ~ 0
100+
VSS
101+
$EndSCHEMATC
Lines changed: 222 additions & 0 deletions
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@@ -0,0 +1,222 @@
1+
(kicad_pcb (version 4) (host pcbnew 4.0.5)
2+
3+
(general
4+
(links 4)
5+
(no_connects 4)
6+
(area 0 0 0 0)
7+
(thickness 1.6)
8+
(drawings 0)
9+
(tracks 0)
10+
(zones 0)
11+
(modules 3)
12+
(nets 5)
13+
)
14+
15+
(page A4)
16+
(layers
17+
(0 F.Cu signal)
18+
(31 B.Cu signal)
19+
(32 B.Adhes user)
20+
(33 F.Adhes user)
21+
(34 B.Paste user)
22+
(35 F.Paste user)
23+
(36 B.SilkS user)
24+
(37 F.SilkS user)
25+
(38 B.Mask user)
26+
(39 F.Mask user)
27+
(40 Dwgs.User user)
28+
(41 Cmts.User user)
29+
(42 Eco1.User user)
30+
(43 Eco2.User user)
31+
(44 Edge.Cuts user)
32+
(45 Margin user)
33+
(46 B.CrtYd user)
34+
(47 F.CrtYd user)
35+
(48 B.Fab user)
36+
(49 F.Fab user)
37+
)
38+
39+
(setup
40+
(last_trace_width 0.25)
41+
(trace_clearance 0.2)
42+
(zone_clearance 0.508)
43+
(zone_45_only no)
44+
(trace_min 0.2)
45+
(segment_width 0.2)
46+
(edge_width 0.15)
47+
(via_size 0.6)
48+
(via_drill 0.4)
49+
(via_min_size 0.4)
50+
(via_min_drill 0.3)
51+
(uvia_size 0.3)
52+
(uvia_drill 0.1)
53+
(uvias_allowed no)
54+
(uvia_min_size 0.2)
55+
(uvia_min_drill 0.1)
56+
(pcb_text_width 0.3)
57+
(pcb_text_size 1.5 1.5)
58+
(mod_edge_width 0.15)
59+
(mod_text_size 1 1)
60+
(mod_text_width 0.15)
61+
(pad_size 1.524 1.524)
62+
(pad_drill 0.762)
63+
(pad_to_mask_clearance 0.2)
64+
(aux_axis_origin 0 0)
65+
(visible_elements FFFFFF7F)
66+
(pcbplotparams
67+
(layerselection 0x00030_80000001)
68+
(usegerberextensions false)
69+
(excludeedgelayer true)
70+
(linewidth 0.100000)
71+
(plotframeref false)
72+
(viasonmask false)
73+
(mode 1)
74+
(useauxorigin false)
75+
(hpglpennumber 1)
76+
(hpglpenspeed 20)
77+
(hpglpendiameter 15)
78+
(hpglpenoverlay 2)
79+
(psnegative false)
80+
(psa4output false)
81+
(plotreference true)
82+
(plotvalue true)
83+
(plotinvisibletext false)
84+
(padsonsilk false)
85+
(subtractmaskfromsilk false)
86+
(outputformat 1)
87+
(mirror false)
88+
(drillshape 1)
89+
(scaleselection 1)
90+
(outputdirectory ""))
91+
)
92+
93+
(net 0 "")
94+
(net 1 "Net-(P1-Pad1)")
95+
(net 2 "Net-(P1-Pad2)")
96+
(net 3 VDD)
97+
(net 4 VSS)
98+
99+
(net_class Default "This is the default net class."
100+
(clearance 0.2)
101+
(trace_width 0.25)
102+
(via_dia 0.6)
103+
(via_drill 0.4)
104+
(uvia_dia 0.3)
105+
(uvia_drill 0.1)
106+
(add_net "Net-(P1-Pad1)")
107+
(add_net "Net-(P1-Pad2)")
108+
(add_net VDD)
109+
(add_net VSS)
110+
)
111+
112+
(module Pin_Headers:Pin_Header_Straight_1x02 (layer F.Cu) (tedit 54EA090C) (tstamp 58868B6D)
113+
(at 145.9992 115.0874 270)
114+
(descr "Through hole pin header")
115+
(tags "pin header")
116+
(path /5886C7CF)
117+
(fp_text reference P1 (at 0 -5.1 270) (layer F.SilkS)
118+
(effects (font (size 1 1) (thickness 0.15)))
119+
)
120+
(fp_text value CONN_01X02 (at 0 -3.1 270) (layer F.Fab)
121+
(effects (font (size 1 1) (thickness 0.15)))
122+
)
123+
(fp_line (start 1.27 1.27) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
124+
(fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15))
125+
(fp_line (start -1.75 -1.75) (end -1.75 4.3) (layer F.CrtYd) (width 0.05))
126+
(fp_line (start 1.75 -1.75) (end 1.75 4.3) (layer F.CrtYd) (width 0.05))
127+
(fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05))
128+
(fp_line (start -1.75 4.3) (end 1.75 4.3) (layer F.CrtYd) (width 0.05))
129+
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
130+
(fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
131+
(fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15))
132+
(fp_line (start -1.27 1.27) (end -1.27 3.81) (layer F.SilkS) (width 0.15))
133+
(fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
134+
(pad 1 thru_hole rect (at 0 0 270) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask)
135+
(net 1 "Net-(P1-Pad1)"))
136+
(pad 2 thru_hole oval (at 0 2.54 270) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask)
137+
(net 2 "Net-(P1-Pad2)"))
138+
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl
139+
(at (xyz 0 -0.05 0))
140+
(scale (xyz 1 1 1))
141+
(rotate (xyz 0 0 90))
142+
)
143+
)
144+
145+
(module Pin_Headers:Pin_Header_Straight_1x02 (layer F.Cu) (tedit 54EA090C) (tstamp 58868B73)
146+
(at 158.623 103.8352)
147+
(descr "Through hole pin header")
148+
(tags "pin header")
149+
(path /5886C74A)
150+
(fp_text reference P2 (at 0 -5.1) (layer F.SilkS)
151+
(effects (font (size 1 1) (thickness 0.15)))
152+
)
153+
(fp_text value CONN_01X02 (at 0 -3.1) (layer F.Fab)
154+
(effects (font (size 1 1) (thickness 0.15)))
155+
)
156+
(fp_line (start 1.27 1.27) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
157+
(fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15))
158+
(fp_line (start -1.75 -1.75) (end -1.75 4.3) (layer F.CrtYd) (width 0.05))
159+
(fp_line (start 1.75 -1.75) (end 1.75 4.3) (layer F.CrtYd) (width 0.05))
160+
(fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05))
161+
(fp_line (start -1.75 4.3) (end 1.75 4.3) (layer F.CrtYd) (width 0.05))
162+
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
163+
(fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
164+
(fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15))
165+
(fp_line (start -1.27 1.27) (end -1.27 3.81) (layer F.SilkS) (width 0.15))
166+
(fp_line (start -1.27 3.81) (end 1.27 3.81) (layer F.SilkS) (width 0.15))
167+
(pad 1 thru_hole rect (at 0 0) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask)
168+
(net 3 VDD))
169+
(pad 2 thru_hole oval (at 0 2.54) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask)
170+
(net 4 VSS))
171+
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl
172+
(at (xyz 0 -0.05 0))
173+
(scale (xyz 1 1 1))
174+
(rotate (xyz 0 0 90))
175+
)
176+
)
177+
178+
(module SMD_Packages:SOIC-14_N (layer F.Cu) (tedit 0) (tstamp 58868B85)
179+
(at 148.5011 105.0036)
180+
(descr "Module CMS SOJ 14 pins Large")
181+
(tags "CMS SOJ")
182+
(path /5886C840)
183+
(attr smd)
184+
(fp_text reference U1 (at 0 -1.27) (layer F.SilkS)
185+
(effects (font (size 1 1) (thickness 0.15)))
186+
)
187+
(fp_text value 4069 (at 0 1.27) (layer F.Fab)
188+
(effects (font (size 1 1) (thickness 0.15)))
189+
)
190+
(fp_line (start 5.08 -2.286) (end 5.08 2.54) (layer F.SilkS) (width 0.15))
191+
(fp_line (start 5.08 2.54) (end -5.08 2.54) (layer F.SilkS) (width 0.15))
192+
(fp_line (start -5.08 2.54) (end -5.08 -2.286) (layer F.SilkS) (width 0.15))
193+
(fp_line (start -5.08 -2.286) (end 5.08 -2.286) (layer F.SilkS) (width 0.15))
194+
(fp_line (start -5.08 -0.508) (end -4.445 -0.508) (layer F.SilkS) (width 0.15))
195+
(fp_line (start -4.445 -0.508) (end -4.445 0.762) (layer F.SilkS) (width 0.15))
196+
(fp_line (start -4.445 0.762) (end -5.08 0.762) (layer F.SilkS) (width 0.15))
197+
(pad 1 smd rect (at -3.81 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask)
198+
(net 2 "Net-(P1-Pad2)"))
199+
(pad 2 smd rect (at -2.54 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask)
200+
(net 1 "Net-(P1-Pad1)"))
201+
(pad 3 smd rect (at -1.27 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
202+
(pad 4 smd rect (at 0 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
203+
(pad 5 smd rect (at 1.27 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
204+
(pad 6 smd rect (at 2.54 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
205+
(pad 7 smd rect (at 3.81 3.302) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask)
206+
(net 4 VSS))
207+
(pad 8 smd rect (at 3.81 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
208+
(pad 9 smd rect (at 2.54 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
209+
(pad 11 smd rect (at 0 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
210+
(pad 12 smd rect (at -1.27 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
211+
(pad 13 smd rect (at -2.54 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
212+
(pad 14 smd rect (at -3.81 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask)
213+
(net 3 VDD))
214+
(pad 10 smd rect (at 1.27 -3.048) (size 0.508 1.143) (layers F.Cu F.Paste F.Mask))
215+
(model SMD_Packages.3dshapes/SOIC-14_N.wrl
216+
(at (xyz 0 0 0))
217+
(scale (xyz 0.5 0.4 0.5))
218+
(rotate (xyz 0 0 0))
219+
)
220+
)
221+
222+
)
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(kicad_pcb (version 4) (host kicad "dummy file") )

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