tests/extmod_hardware/machine_uart_irq_rxidle.py: Test multiple writes.

This tests that the RXIDLE callback is called correctly after a second lot
of bytes are received.

Signed-off-by: Damien George <[email protected]>

Author: dpgeorge

tests/extmod_hardware/machine_uart_irq_rxidle.py

@@ -64,10 +64,13 @@ def irq(u):
     print("IRQ_RXIDLE:", bool(u.irq().flags() & u.IRQ_RXIDLE), "data:", u.read())
 
 
-text = "12345678"
+text = ("12345678", "abcdefgh")
 
 # Test that the IRQ is called for each set of byte received.
 for bits_per_s in (2400, 9600, 115200):
+    print("========")
+    print("bits_per_s:", bits_per_s)
+
     if tx_pin is None:
         uart = UART(uart_id, bits_per_s)
     else:
@@ -81,10 +84,11 @@ def irq(u):
     # Configure desired IRQ.
     uart.irq(irq, uart.IRQ_RXIDLE)
 
-    # Write data and wait for IRQ.
-    print("write", bits_per_s)
-    uart.write(text)
-    uart.flush()
-    print("ready")
-    time.sleep_ms(100)
-    print("done")
+    for i in range(2):
+        # Write data and wait for IRQ.
+        print("write")
+        uart.write(text[i])
+        uart.flush()
+        print("ready")
+        time.sleep_ms(100)
+        print("done")

tests/extmod_hardware/machine_uart_irq_rxidle.py.exp

@@ -1,12 +1,30 @@
-write 2400
+========
+bits_per_s: 2400
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
-write 9600
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 9600
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
-write 115200
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done
+========
+bits_per_s: 115200
+write
 ready
 IRQ_RXIDLE: True data: b'12345678'
 done
+write
+ready
+IRQ_RXIDLE: True data: b'abcdefgh'
+done