Skip to content

Commit 3189e49

Browse files
dpgeorgedpgeorge
committed
stm32/boards/OPENMV_N6: Add new board definition files.
Signed-off-by: Damien George <[email protected]>
1 parent 7016900 commit 3189e49

File tree

9 files changed

+576
-0
lines changed

9 files changed

+576
-0
lines changed

‎ports/stm32/boards/OPENMV_N6/bdev.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2025 Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "storage.h"
28+
#include "xspi.h"
29+
30+
#if MICROPY_HW_SPIFLASH_ENABLE_CACHE
31+
#error "Cannot enable MICROPY_HW_SPIFLASH_ENABLE_CACHE"
32+
#endif
33+
34+
// External SPI flash uses hardware XSPI interface.
35+
const mp_spiflash_config_t spiflash_config = {
36+
.bus_kind = MP_SPIFLASH_BUS_QSPI,
37+
.bus.u_qspi.data = (void *)&xspi_flash2,
38+
.bus.u_qspi.proto = &xspi_proto,
39+
};
40+
41+
spi_bdev_t spi_bdev;

‎ports/stm32/boards/OPENMV_N6/board.c

Lines changed: 131 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,131 @@
1+
/*
2+
* This file is part of the MicroPython project, http://micropython.org/
3+
*
4+
* The MIT License (MIT)
5+
*
6+
* Copyright (c) 2024-2025 Damien P. George
7+
*
8+
* Permission is hereby granted, free of charge, to any person obtaining a copy
9+
* of this software and associated documentation files (the "Software"), to deal
10+
* in the Software without restriction, including without limitation the rights
11+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12+
* copies of the Software, and to permit persons to whom the Software is
13+
* furnished to do so, subject to the following conditions:
14+
*
15+
* The above copyright notice and this permission notice shall be included in
16+
* all copies or substantial portions of the Software.
17+
*
18+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24+
* THE SOFTWARE.
25+
*/
26+
27+
#include "py/mphal.h"
28+
#include "boardctrl.h"
29+
#include "xspi.h"
30+
31+
// Values for OTP fuses for VDDIO2/3, to select low voltage mode (<2.5V).
32+
// See RM0486, Section 5, Table 18.
33+
#define BSEC_HW_CONFIG_ID (124U)
34+
#define BSEC_HWS_HSLV_VDDIO3 (1U << 15)
35+
#define BSEC_HWS_HSLV_VDDIO2 (1U << 16)
36+
37+
#define OMV_BOOT_MAGIC_ADDR (0x3401FFFCU)
38+
#define OMV_BOOT_MAGIC_VALUE (0xB00710ADU)
39+
40+
void mboot_board_early_init(void) {
41+
// TODO: move some of the below code to a common location for all N6 boards?
42+
43+
// Enable PWR, BSEC and SYSCFG clocks.
44+
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
45+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
46+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
47+
48+
// Program high speed IO optimization fuses if they aren't already set.
49+
uint32_t fuse;
50+
BSEC_HandleTypeDef hbsec = { .Instance = BSEC };
51+
const uint32_t mask = BSEC_HWS_HSLV_VDDIO2 | BSEC_HWS_HSLV_VDDIO3;
52+
if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
53+
fuse = 0;
54+
} else if ((fuse & mask) != mask) {
55+
// Program the fuse, and read back the set value.
56+
if (HAL_BSEC_OTP_Program(&hbsec, BSEC_HW_CONFIG_ID, fuse | mask, HAL_BSEC_NORMAL_PROG) != HAL_OK) {
57+
fuse = 0;
58+
} else if (HAL_BSEC_OTP_Read(&hbsec, BSEC_HW_CONFIG_ID, &fuse) != HAL_OK) {
59+
fuse = 0;
60+
}
61+
}
62+
63+
// Enable Vdd ADC, needed for the ADC to work.
64+
LL_PWR_EnableVddADC();
65+
66+
// Configure VDDIO2. Only enable 1.8V mode if the fuse is set.
67+
LL_PWR_EnableVddIO2();
68+
if (fuse & BSEC_HWS_HSLV_VDDIO2) {
69+
LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
70+
}
71+
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
72+
73+
// Configure VDDIO3. Only enable 1.8V mode if the fuse is set.
74+
LL_PWR_EnableVddIO3();
75+
if (fuse & BSEC_HWS_HSLV_VDDIO3) {
76+
LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
77+
}
78+
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
79+
80+
// Configure VDDIO4.
81+
LL_PWR_EnableVddIO4();
82+
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
83+
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
84+
85+
// Enable VDD for ADC and USB.
86+
LL_PWR_EnableVddADC();
87+
LL_PWR_EnableVddUSB();
88+
89+
// Enable XSPI in memory-mapped mode.
90+
xspi_init();
91+
}
92+
93+
void board_enter_bootloader(unsigned int n_args, const void *args) {
94+
// Support both OpenMV bootloader and mboot.
95+
*((uint32_t *)OMV_BOOT_MAGIC_ADDR) = OMV_BOOT_MAGIC_VALUE;
96+
SCB_CleanDCache();
97+
boardctrl_maybe_enter_mboot(n_args, args);
98+
}
99+
100+
void board_early_init(void) {
101+
// TODO: if (HAL_PWREx_ConfigSupply(PWR_EXTERNAL_SOURCE_SUPPLY ) != HAL_OK)
102+
103+
LL_PWR_EnableWakeUpPin(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2);
104+
LL_PWR_SetWakeUpPinPolarityLow(LL_PWR_WAKEUP_PIN3 | LL_PWR_WAKEUP_PIN2);
105+
}
106+
107+
void board_leave_standby(void) {
108+
// TODO: move some of the below code to a common location for all N6 boards?
109+
110+
// Enable PWR, BSEC and SYSCFG clocks.
111+
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
112+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_BSEC);
113+
LL_APB4_GRP2_EnableClock(LL_APB4_GRP2_PERIPH_SYSCFG);
114+
115+
// Configure VDDIO2 (1.8V mode selection is retained).
116+
LL_PWR_EnableVddIO2();
117+
SYSCFG->VDDIO2CCCR |= SYSCFG_VDDIO2CCCR_EN; // enable IO compensation
118+
119+
// Configure VDDIO3 (1.8V mode selection is retained).
120+
LL_PWR_EnableVddIO3();
121+
SYSCFG->VDDIO3CCCR |= SYSCFG_VDDIO3CCCR_EN; // enable IO compensation
122+
123+
// Configure VDDIO4.
124+
LL_PWR_EnableVddIO4();
125+
LL_PWR_SetVddIO4VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_3V3);
126+
SYSCFG->VDDIO4CCCR |= SYSCFG_VDDIO4CCCR_EN; // enable IO compensation
127+
128+
// Enable VDD for ADC and USB.
129+
LL_PWR_EnableVddADC();
130+
LL_PWR_EnableVddUSB();
131+
}

‎ports/stm32/boards/OPENMV_N6/board.ld

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
/*
2+
Linker script for OPENMV_N6.
3+
4+
Note: upper 512k of SRAM2 is copied from external flash upon reset.
5+
*/
6+
7+
/* Specify the memory areas */
8+
MEMORY
9+
{
10+
FLEXRAM_S (xrw) : ORIGIN = 0x34000000, LENGTH = 80K
11+
SRAM2_S_RAM (xrw) : ORIGIN = 0x34100000, LENGTH = 1024K
12+
SRAM2_S_FSBL (xrw) : ORIGIN = 0x34180400, LENGTH = 511K /* mboot firmware, not needed after mboot exits */
13+
EXT_FLASH (rx) : ORIGIN = 0x70080000, LENGTH = 3584K
14+
EXT_FLASH_FS (rx) : ORIGIN = 0x70400000, LENGTH = 4M
15+
EXT_FLASH_ROMFS (rx) : ORIGIN = 0x70800000, LENGTH = 24M
16+
}
17+
18+
REGION_ALIAS("IRAM", FLEXRAM_S);
19+
REGION_ALIAS("RAM", SRAM2_S_RAM);
20+
REGION_ALIAS("FLASH_APP", EXT_FLASH);
21+
22+
/* produce a link error if there is not this amount of RAM for these sections */
23+
_minimum_stack_size = 2K;
24+
_minimum_heap_size = 16K;
25+
26+
/* Define the stack. The stack is full descending so begins just above last byte
27+
of RAM. Note that EABI requires the stack to be 8-byte aligned for a call. */
28+
_estack = ORIGIN(RAM) + LENGTH(RAM) - _estack_reserve;
29+
_sstack = _estack - 16K; /* tunable */
30+
31+
/* RAM extents for the garbage collector */
32+
_ram_start = ORIGIN(RAM);
33+
_ram_end = ORIGIN(RAM) + LENGTH(RAM);
34+
_heap_start = _ebss; /* heap starts just after statically allocated memory */
35+
_heap_end = _sstack;
36+
37+
/* ROMFS location */
38+
_micropy_hw_romfs_part0_start = ORIGIN(EXT_FLASH_ROMFS);
39+
_micropy_hw_romfs_part0_size = LENGTH(EXT_FLASH_ROMFS);

‎ports/stm32/boards/OPENMV_N6/manifest.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
1+
include("$(PORT_DIR)/boards/manifest.py")
2+
require("bundle-networking")
3+
require("aioble")

‎ports/stm32/boards/OPENMV_N6/mpconfigboard.h

Lines changed: 167 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,167 @@
1+
#define MICROPY_HW_BOARD_NAME "OpenMV N6"
2+
#define MICROPY_HW_MCU_NAME "STM32N657X0"
3+
4+
#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t
5+
#define MICROPY_ALLOC_GC_STACK_SIZE (128)
6+
#define MICROPY_FATFS_EXFAT (1)
7+
8+
#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (0)
9+
#define MICROPY_HW_HAS_SWITCH (0)
10+
#define MICROPY_HW_HAS_FLASH (1)
11+
#define MICROPY_HW_SDCARD_MOUNT_AT_BOOT (0)
12+
#define MICROPY_HW_ENABLE_RNG (1)
13+
#define MICROPY_HW_ENABLE_RTC (1)
14+
#define MICROPY_HW_ENABLE_DAC (0)
15+
#define MICROPY_HW_ENABLE_USB (1)
16+
#define MICROPY_HW_ENABLE_SDCARD (1)
17+
#define MICROPY_PY_PYB_LEGACY (0)
18+
19+
#define MICROPY_BOARD_ENTER_BOOTLOADER board_enter_bootloader
20+
#define MICROPY_BOARD_EARLY_INIT board_early_init
21+
#define MICROPY_BOARD_LEAVE_STANDBY board_leave_standby()
22+
23+
// HSE is 48MHz, this gives a CPU frequency of 800MHz.
24+
#define MICROPY_HW_CLK_PLLM (6)
25+
#define MICROPY_HW_CLK_PLLN (100)
26+
#define MICROPY_HW_CLK_PLLP1 (1)
27+
#define MICROPY_HW_CLK_PLLP2 (1)
28+
#define MICROPY_HW_CLK_PLLFRAC (0)
29+
30+
// The LSE is a 32kHz crystal.
31+
#define MICROPY_HW_RTC_USE_LSE (1)
32+
#define MICROPY_HW_RTC_USE_US (1)
33+
34+
// External SPI flash.
35+
#define MICROPY_HW_XSPIFLASH_SIZE_BITS_LOG2 (28) // 256Mbit
36+
37+
// ROMFS config
38+
#define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_XSPI (1)
39+
#define MICROPY_HW_ROMFS_XSPI_SPIBDEV_OBJ (&spi_bdev)
40+
#define MICROPY_HW_ROMFS_ENABLE_PART0 (1)
41+
42+
// SPI flash, block device config.
43+
#define MICROPY_HW_BDEV_SPIFLASH (&spi_bdev)
44+
#define MICROPY_HW_BDEV_SPIFLASH_EXTENDED (&spi_bdev)
45+
#define MICROPY_HW_BDEV_SPIFLASH_CONFIG (&spiflash_config)
46+
#define MICROPY_HW_BDEV_SPIFLASH_OFFSET_BYTES (4 * 1024 * 1024)
47+
#define MICROPY_HW_BDEV_SPIFLASH_SIZE_BYTES (4 * 1024 * 1024)
48+
49+
// UART buses
50+
#define MICROPY_HW_UART2_TX (pyb_pin_BT_TXD)
51+
#define MICROPY_HW_UART2_RX (pyb_pin_BT_RXD)
52+
#define MICROPY_HW_UART2_RTS (pyb_pin_BT_RTS)
53+
#define MICROPY_HW_UART2_CTS (pyb_pin_BT_CTS)
54+
#define MICROPY_HW_UART3_TX (pyb_pin_UART3_TX)
55+
#define MICROPY_HW_UART3_RX (pyb_pin_UART3_RX)
56+
#define MICROPY_HW_UART4_TX (pyb_pin_UART4_TX)
57+
#define MICROPY_HW_UART4_RX (pyb_pin_UART4_RX)
58+
#define MICROPY_HW_UART7_TX (pyb_pin_UART7_TX)
59+
#define MICROPY_HW_UART7_RX (pyb_pin_UART7_RX)
60+
61+
// I2C buses
62+
#define MICROPY_HW_I2C2_SCL (pyb_pin_I2C2_SCL)
63+
#define MICROPY_HW_I2C2_SDA (pyb_pin_I2C2_SDA)
64+
#define MICROPY_HW_I2C4_SCL (pyb_pin_I2C4_SCL)
65+
#define MICROPY_HW_I2C4_SDA (pyb_pin_I2C4_SDA)
66+
67+
// SPI buses
68+
#define MICROPY_HW_SPI2_NSS (pyb_pin_SPI2_CS)
69+
#define MICROPY_HW_SPI2_SCK (pyb_pin_SPI2_SCK)
70+
#define MICROPY_HW_SPI2_MISO (pyb_pin_SPI2_MISO)
71+
#define MICROPY_HW_SPI2_MOSI (pyb_pin_SPI2_MOSI)
72+
#define MICROPY_HW_SPI4_NSS (pyb_pin_SPI4_CS)
73+
#define MICROPY_HW_SPI4_SCK (pyb_pin_SPI4_SCK)
74+
#define MICROPY_HW_SPI4_MISO (pyb_pin_SPI4_MISO)
75+
#define MICROPY_HW_SPI4_MOSI (pyb_pin_SPI4_MOSI)
76+
77+
// USER is pulled high, and pressing the button makes the input go low.
78+
#define MICROPY_HW_USRSW_PIN (pyb_pin_BUTTON)
79+
#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL)
80+
#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING)
81+
#define MICROPY_HW_USRSW_PRESSED (0)
82+
83+
// LEDs
84+
#define MICROPY_HW_LED1 (pyb_pin_LED_RED)
85+
#define MICROPY_HW_LED2 (pyb_pin_LED_GREEN)
86+
#define MICROPY_HW_LED3 (pyb_pin_LED_BLUE)
87+
#define MICROPY_HW_LED_ON(pin) (mp_hal_pin_low(pin))
88+
#define MICROPY_HW_LED_OFF(pin) (mp_hal_pin_high(pin))
89+
90+
// SD Card SDMMC
91+
// SD_VSELECT: low(default)=3.3V IO, high=1.8V IO
92+
// SD_RESET: drive low to turn off SD VCC (pulled high by default)
93+
// SD_DETECT: pulled high in hardware, goes low when SD inserted
94+
#define MICROPY_HW_SDCARD_SDMMC (1)
95+
#define MICROPY_HW_SDCARD_CK (pyb_pin_SD_SDIO_CK)
96+
#define MICROPY_HW_SDCARD_CMD (pyb_pin_SD_SDIO_CMD)
97+
#define MICROPY_HW_SDCARD_D0 (pyb_pin_SD_SDIO_D0)
98+
#define MICROPY_HW_SDCARD_D1 (pyb_pin_SD_SDIO_D1)
99+
#define MICROPY_HW_SDCARD_D2 (pyb_pin_SD_SDIO_D2)
100+
#define MICROPY_HW_SDCARD_D3 (pyb_pin_SD_SDIO_D3)
101+
#define MICROPY_HW_SDCARD_DETECT_PIN (pyb_pin_SD_DETECT)
102+
#define MICROPY_HW_SDCARD_DETECT_PULL (GPIO_NOPULL)
103+
#define MICROPY_HW_SDCARD_DETECT_PRESENT (GPIO_PIN_RESET)
104+
105+
// WiFi SDMMC
106+
#define MICROPY_HW_SDIO_SDMMC (2)
107+
#define MICROPY_HW_SDIO_CK (pyb_pin_WL_SDIO_CK)
108+
#define MICROPY_HW_SDIO_CMD (pyb_pin_WL_SDIO_CMD)
109+
#define MICROPY_HW_SDIO_D0 (pyb_pin_WL_SDIO_D0)
110+
#define MICROPY_HW_SDIO_D1 (pyb_pin_WL_SDIO_D1)
111+
#define MICROPY_HW_SDIO_D2 (pyb_pin_WL_SDIO_D2)
112+
#define MICROPY_HW_SDIO_D3 (pyb_pin_WL_SDIO_D3)
113+
114+
// USB config
115+
#define MICROPY_HW_USB_HS (1)
116+
#define MICROPY_HW_USB_HS_IN_FS (1)
117+
#define MICROPY_HW_USB_MAIN_DEV (USB_PHY_HS_ID)
118+
#define MICROPY_HW_USB_VID 0x37C5
119+
#define MICROPY_HW_USB_PID 0x1206
120+
#define MICROPY_HW_USB_PID_CDC (MICROPY_HW_USB_PID)
121+
#define MICROPY_HW_USB_PID_MSC (MICROPY_HW_USB_PID)
122+
#define MICROPY_HW_USB_PID_CDC_MSC (MICROPY_HW_USB_PID)
123+
#define MICROPY_HW_USB_PID_CDC_HID (MICROPY_HW_USB_PID)
124+
#define MICROPY_HW_USB_PID_CDC_MSC_HID (MICROPY_HW_USB_PID)
125+
126+
// Murata 1YN configuration
127+
#define CYW43_CHIPSET_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/w43439_sdio_1yn_7_95_59_combined.h"
128+
#define CYW43_WIFI_NVRAM_INCLUDE_FILE "lib/cyw43-driver/firmware/wifi_nvram_1yn.h"
129+
#define CYW43_BT_FIRMWARE_INCLUDE_FILE "lib/cyw43-driver/firmware/cyw43_btfw_1yn.h"
130+
131+
// Bluetooth config
132+
#define MICROPY_HW_BLE_UART_ID (PYB_UART_2)
133+
#define MICROPY_HW_BLE_UART_BAUDRATE (115200)
134+
#define MICROPY_HW_BLE_UART_BAUDRATE_SECONDARY (3000000)
135+
#define MICROPY_HW_BLE_UART_BAUDRATE_DOWNLOAD_FIRMWARE (3000000)
136+
137+
/******************************************************************************/
138+
// Bootloader configuration
139+
140+
#define MBOOT_BOARD_EARLY_INIT(initial_r0) mboot_board_early_init()
141+
142+
#define MBOOT_FSLOAD (1)
143+
#define MBOOT_VFS_FAT (1)
144+
145+
#define MBOOT_SPIFLASH_CS (pyb_pin_XSPIM_P2_CS)
146+
#define MBOOT_SPIFLASH_SCK (pyb_pin_XSPIM_P2_SCK)
147+
#define MBOOT_SPIFLASH_MOSI (pyb_pin_XSPIM_P2_IO0)
148+
#define MBOOT_SPIFLASH_MISO (pyb_pin_XSPIM_P2_IO1)
149+
#define MBOOT_SPIFLASH_ADDR (0x70000000)
150+
#define MBOOT_SPIFLASH_BYTE_SIZE (32 * 1024 * 1024)
151+
#define MBOOT_SPIFLASH_LAYOUT "/0x70000000/8192*4Kg"
152+
#define MBOOT_SPIFLASH_ERASE_BLOCKS_PER_PAGE (1)
153+
#define MBOOT_SPIFLASH_SPIFLASH (&spi_bdev.spiflash)
154+
#define MBOOT_SPIFLASH_CONFIG (&spiflash_config)
155+
156+
/******************************************************************************/
157+
// Function and variable declarations
158+
159+
extern const struct _mp_spiflash_config_t spiflash_config;
160+
extern struct _spi_bdev_t spi_bdev;
161+
162+
void mboot_board_early_init(void);
163+
void mboot_board_entry_init(void);
164+
165+
void board_enter_bootloader(unsigned int n_args, const void *args);
166+
void board_early_init(void);
167+
void board_leave_standby(void);

0 commit comments

Comments
 (0)