ports/rp2: Further PSRAM setup tweaks.

Move PSRAM setup to immediately after flash timing setup.
Disable interrupts while setting up PSRAM.

Signed-off-by: Mike Bell <[email protected]>

Author: MichaelBell

ports/rp2/main.c

@@ -86,10 +86,6 @@ int main(int argc, char **argv) {
     SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
     #endif
 
-    #if defined(MICROPY_HW_PSRAM_CS_PIN) && MICROPY_HW_ENABLE_PSRAM
-    size_t psram_size = psram_init(MICROPY_HW_PSRAM_CS_PIN);
-    #endif
-
     pendsv_init();
     soft_timer_init();
 
@@ -102,6 +98,10 @@ int main(int argc, char **argv) {
     // Set the flash divisor to an appropriate value
     rp2_flash_set_timing();
 
+    #if defined(MICROPY_HW_PSRAM_CS_PIN) && MICROPY_HW_ENABLE_PSRAM
+    size_t psram_size = psram_init(MICROPY_HW_PSRAM_CS_PIN);
+    #endif
+
     #if MICROPY_HW_ENABLE_UART_REPL
     bi_decl(bi_program_feature("UART REPL"))
     setup_default_uart();

ports/rp2/rp2_psram.c

@@ -9,8 +9,6 @@
 size_t __no_inline_not_in_flash_func(psram_detect)() {
     int psram_size = 0;
 
-    uint32_t intr_stash = save_and_disable_interrupts();
-
     // Try and read the PSRAM ID via direct_csr.
     qmi_hw->direct_csr = 30 << QMI_DIRECT_CSR_CLKDIV_LSB | QMI_DIRECT_CSR_EN_BITS;
 
@@ -76,13 +74,14 @@ size_t __no_inline_not_in_flash_func(psram_detect)() {
         }
     }
 
-    restore_interrupts(intr_stash);
     return psram_size;
 }
 
 size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
     gpio_set_function(cs_pin, GPIO_FUNC_XIP_CS1);
 
+    uint32_t intr_stash = save_and_disable_interrupts();
+
     size_t psram_size = psram_detect();
 
     if (!psram_size) {
@@ -162,5 +161,7 @@ size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
     // Enable writes to PSRAM
     hw_set_bits(&xip_ctrl_hw->ctrl, XIP_CTRL_WRITABLE_M1_BITS);
 
+    restore_interrupts(intr_stash);
+
     return psram_size;
 }