|
| 1 | +/* |
| 2 | + * This file is part of the MicroPython project, http://micropython.org/ |
| 3 | + * |
| 4 | + * The MIT License (MIT) |
| 5 | + * |
| 6 | + * Copyright (c) 2020-2021 Damien P. George |
| 7 | + * Copyright (c) 2022-2025 Robert Hammelrath |
| 8 | + * |
| 9 | + * Permission is hereby granted, free of charge, to any person obtaining a copy |
| 10 | + * of this software and associated documentation files (the "Software"), to deal |
| 11 | + * in the Software without restriction, including without limitation the rights |
| 12 | + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
| 13 | + * copies of the Software, and to permit persons to whom the Software is |
| 14 | + * furnished to do so, subject to the following conditions: |
| 15 | + * |
| 16 | + * The above copyright notice and this permission notice shall be included in |
| 17 | + * all copies or substantial portions of the Software. |
| 18 | + * |
| 19 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 20 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 21 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
| 22 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 23 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 24 | + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
| 25 | + * THE SOFTWARE. |
| 26 | + */ |
| 27 | + |
| 28 | +#include "py/runtime.h" |
| 29 | +#include "samd_soc.h" |
| 30 | +#include "pin_af.h" |
| 31 | +#include "genhdr/pins.h" |
| 32 | + |
| 33 | +#define TRANSMIT (1) |
| 34 | +#define RECEIVE (0) |
| 35 | +#define NACK_RECVD (i2c->I2CS.STATUS.bit.RXNACK == 1) |
| 36 | +#define IRQ_AMATCH (i2c->I2CS.INTFLAG.bit.AMATCH == 1) |
| 37 | +#define IRQ_DRDY (i2c->I2CS.INTFLAG.bit.DRDY == 1) |
| 38 | +#define IRQ_STOP (i2c->I2CS.INTFLAG.bit.PREC == 1) |
| 39 | + |
| 40 | +#define PREPARE_ACK i2c->I2CS.CTRLB.bit.ACKACT = 0 |
| 41 | +#define PREPARE_NACK i2c->I2CS.CTRLB.bit.ACKACT = 1 |
| 42 | + |
| 43 | +typedef struct _machine_i2c_target_obj_t { |
| 44 | + mp_obj_base_t base; |
| 45 | + Sercom *instance; |
| 46 | + uint8_t id; |
| 47 | + uint8_t scl; |
| 48 | + uint8_t sda; |
| 49 | + uint8_t addr; |
| 50 | + uint8_t direction; |
| 51 | +} machine_i2c_target_obj_t; |
| 52 | + |
| 53 | +void common_i2c_target_irq_handler(int i2c_id) { |
| 54 | + // Handle Sercom I2C IRQ for target memory mode. |
| 55 | + machine_i2c_target_obj_t *self = MP_STATE_PORT(sercom_table[i2c_id]); |
| 56 | + machine_i2c_target_data_t *data = &machine_i2c_target_data[i2c_id]; |
| 57 | + |
| 58 | + if (self != NULL) { |
| 59 | + Sercom *i2c = self->instance; |
| 60 | + |
| 61 | + if (IRQ_AMATCH) { |
| 62 | + // Address match. |
| 63 | + self->direction = i2c->I2CS.STATUS.bit.DIR; |
| 64 | + machine_i2c_target_data_addr_match(data, self->direction); |
| 65 | + // Send ACK |
| 66 | + i2c->I2CS.CTRLB.bit.CMD = 3; |
| 67 | + |
| 68 | + } else if (IRQ_DRDY) { |
| 69 | + // Data to be handled, depending in the direction |
| 70 | + if (self->direction == TRANSMIT) { |
| 71 | + machine_i2c_target_data_read_request(self, data); |
| 72 | + } else { |
| 73 | + machine_i2c_target_data_write_request(self, data); |
| 74 | + } |
| 75 | + // ACK will be sent in mp_machine_i2c_target_read_bytes/mp_machine_i2c_target_write_bytes. |
| 76 | + } else if (IRQ_STOP) { |
| 77 | + // Stop detected. Just reset the data machine. |
| 78 | + machine_i2c_target_data_stop(data); |
| 79 | + i2c->I2CS.INTFLAG.reg |= SERCOM_I2CS_INTFLAG_PREC; |
| 80 | + |
| 81 | + } else { // On any error clear the interrupts and reset the data state. |
| 82 | + machine_i2c_target_data_stop(data); |
| 83 | + i2c->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR | SERCOM_I2CS_INTFLAG_AMATCH | |
| 84 | + SERCOM_I2CS_INTFLAG_DRDY | SERCOM_I2CS_INTFLAG_PREC; |
| 85 | + } |
| 86 | + } |
| 87 | +} |
| 88 | + |
| 89 | +/******************************************************************************/ |
| 90 | +// I2CTarget port implementation |
| 91 | + |
| 92 | +static inline size_t mp_machine_i2c_target_get_index(machine_i2c_target_obj_t *self) { |
| 93 | + return self->id; |
| 94 | +} |
| 95 | + |
| 96 | +static void mp_machine_i2c_target_event_callback(machine_i2c_target_irq_obj_t *irq) { |
| 97 | + mp_irq_handler(&irq->base); |
| 98 | +} |
| 99 | + |
| 100 | +static size_t mp_machine_i2c_target_read_bytes(machine_i2c_target_obj_t *self, size_t len, uint8_t *buf) { |
| 101 | + Sercom *i2c = self->instance; |
| 102 | + buf[0] = i2c->I2CS.DATA.reg; |
| 103 | + i2c->I2CS.CTRLB.bit.CMD = 3; // send ACK |
| 104 | + return 1; |
| 105 | +} |
| 106 | + |
| 107 | +static size_t mp_machine_i2c_target_write_bytes(machine_i2c_target_obj_t *self, size_t len, const uint8_t *buf) { |
| 108 | + Sercom *i2c = self->instance; |
| 109 | + i2c->I2CS.DATA.reg = buf[0]; |
| 110 | + i2c->I2CS.CTRLB.bit.CMD = 3; // send ACK |
| 111 | + return 1; |
| 112 | +} |
| 113 | + |
| 114 | +static inline void mp_machine_i2c_target_irq_config(machine_i2c_target_obj_t *self, unsigned int trigger) { |
| 115 | + (void)self; |
| 116 | + (void)trigger; |
| 117 | +} |
| 118 | + |
| 119 | +mp_obj_t mp_machine_i2c_target_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { |
| 120 | + enum { ARG_id, ARG_addr, ARG_addrsize, ARG_mem, ARG_mem_addrsize, ARG_scl, ARG_sda }; |
| 121 | + static const mp_arg_t allowed_args[] = { |
| 122 | + #if MICROPY_HW_DEFAULT_I2C_ID < 0 |
| 123 | + { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = -1} }, |
| 124 | + #else |
| 125 | + { MP_QSTR_id, MP_ARG_INT, {.u_int = MICROPY_HW_DEFAULT_I2C_ID} }, |
| 126 | + #endif |
| 127 | + { MP_QSTR_addr, MP_ARG_REQUIRED | MP_ARG_INT }, |
| 128 | + { MP_QSTR_addrsize, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 7} }, |
| 129 | + { MP_QSTR_mem, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, |
| 130 | + { MP_QSTR_mem_addrsize, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 8} }, |
| 131 | + #if defined(pin_SCL) && defined(pin_SDA) |
| 132 | + { MP_QSTR_scl, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = pin_SCL} }, |
| 133 | + { MP_QSTR_sda, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = pin_SDA} }, |
| 134 | + #else |
| 135 | + { MP_QSTR_scl, MP_ARG_REQUIRED | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, |
| 136 | + { MP_QSTR_sda, MP_ARG_REQUIRED | MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, |
| 137 | + #endif |
| 138 | + }; |
| 139 | + |
| 140 | + // Parse args. |
| 141 | + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; |
| 142 | + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); |
| 143 | + |
| 144 | + // Get I2C bus. |
| 145 | + int id = args[ARG_id].u_int; |
| 146 | + if (id < 0 || id >= SERCOM_INST_NUM) { |
| 147 | + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("I2C(%d) doesn't exist"), id); |
| 148 | + } |
| 149 | + |
| 150 | + // Get the peripheral object. |
| 151 | + machine_i2c_target_obj_t *self = mp_obj_malloc_with_finaliser(machine_i2c_target_obj_t, &machine_i2c_target_type); |
| 152 | + self->id = id; |
| 153 | + self->instance = sercom_instance[id]; |
| 154 | + |
| 155 | + // Set SCL/SDA pins. |
| 156 | + self->sda = pin_config_for_i2c(args[ARG_sda].u_obj, id, 0); |
| 157 | + self->scl = pin_config_for_i2c(args[ARG_scl].u_obj, id, 1); |
| 158 | + |
| 159 | + MP_STATE_PORT(sercom_table[id]) = self; |
| 160 | + |
| 161 | + // Get the address and initialise data. |
| 162 | + self->addr = args[ARG_addr].u_int; |
| 163 | + MP_STATE_PORT(machine_i2c_target_mem_obj)[id] = args[ARG_mem].u_obj; |
| 164 | + machine_i2c_target_data_t *data = &machine_i2c_target_data[id]; |
| 165 | + machine_i2c_target_data_init(data, args[ARG_mem].u_obj, args[ARG_mem_addrsize].u_int); |
| 166 | + |
| 167 | + // Set up the clocks |
| 168 | + enable_sercom_clock(id); |
| 169 | + |
| 170 | + // Initialise the I2C peripheral |
| 171 | + Sercom *i2c = self->instance; |
| 172 | + // Reset the device |
| 173 | + i2c->I2CS.CTRLA.reg = SERCOM_I2CM_CTRLA_SWRST; |
| 174 | + while (i2c->I2CS.SYNCBUSY.bit.SWRST == 1) { |
| 175 | + } |
| 176 | + |
| 177 | + // Set to slave mode, enable SCl timeout, set the address |
| 178 | + i2c->I2CS.CTRLA.reg = SERCOM_I2CS_CTRLA_MODE(0x04) |
| 179 | + | SERCOM_I2CS_CTRLA_SEXTTOEN | SERCOM_I2CS_CTRLA_LOWTOUTEN; |
| 180 | + i2c->I2CS.ADDR.reg = self->addr << 1; |
| 181 | + |
| 182 | + // Enable interrupts |
| 183 | + sercom_register_irq(id, &common_i2c_target_irq_handler); |
| 184 | + #if defined(MCU_SAMD21) |
| 185 | + NVIC_EnableIRQ(SERCOM0_IRQn + id); |
| 186 | + #elif defined(MCU_SAMD51) |
| 187 | + NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id); |
| 188 | + NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 1); |
| 189 | + NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 2); |
| 190 | + NVIC_EnableIRQ(SERCOM0_0_IRQn + 4 * id + 3); |
| 191 | + #endif |
| 192 | + i2c->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY | SERCOM_I2CS_INTENSET_AMATCH | |
| 193 | + SERCOM_I2CS_INTENSET_PREC | SERCOM_I2CS_INTENSET_ERROR; |
| 194 | + |
| 195 | + // Now enable I2C. |
| 196 | + sercom_enable(i2c, 1); |
| 197 | + |
| 198 | + return MP_OBJ_FROM_PTR(self); |
| 199 | +} |
| 200 | + |
| 201 | +static void mp_machine_i2c_target_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { |
| 202 | + machine_i2c_target_obj_t *self = MP_OBJ_TO_PTR(self_in); |
| 203 | + mp_printf(print, "I2C(%u, scl=\"%q\", sda=\"%q\", addr=%u)", |
| 204 | + self->id, pin_find_by_id(self->scl)->name, pin_find_by_id(self->sda)->name, |
| 205 | + self->addr); |
| 206 | +} |
| 207 | + |
| 208 | +// Stop the Slave transfer and free the memory objects. |
| 209 | +static void mp_machine_i2c_target_deinit(machine_i2c_target_obj_t *self) { |
| 210 | + // Disable I2C |
| 211 | + sercom_enable(self->instance, 0); |
| 212 | + MP_STATE_PORT(sercom_table[self->id]) = NULL; |
| 213 | +} |
0 commit comments