ports/rp2: Compute QMI timing based on system clock.

Signed-off-by: Mike Bell <[email protected]>

Author: MichaelBell

ports/rp2/rp2_psram.c

@@ -12,13 +12,15 @@ void __no_inline_not_in_flash_func(psram_set_qmi_timing)() {
         ;
     }
 
-    if (clock_get_hz(clk_sys) > 133000000) {
-        // For > 133 MHz
-        qmi_hw->m[0].timing = 0x40000202;
-    } else {
-        // For <= 133 MHz
-        qmi_hw->m[0].timing = 0x40000101;
-    }
+    // Use the minimum divisor assuming a 133MHz flash.
+    // RX delay equal to the divisor means sampling at the same time as the next falling edge of SCK after the
+    // falling edge that generated the data.  This is pretty tight at 133MHz but seems to work with the Winbond flash chips.
+    const int max_flash_freq = 133000000;
+    const int divisor = (clock_get_hz(clk_sys) + max_flash_freq - 1) / max_flash_freq;
+    const int rxdelay = divisor;
+    qmi_hw->m[0].timing = (1 << QMI_M0_TIMING_COOLDOWN_LSB) |
+        rxdelay << QMI_M1_TIMING_RXDELAY_LSB |
+        divisor << QMI_M1_TIMING_CLKDIV_LSB;
 
     // Force a read through XIP to ensure the timing is applied
     volatile uint32_t *ptr = (volatile uint32_t *)0x14000000;
@@ -126,30 +128,35 @@ size_t __no_inline_not_in_flash_func(psram_init)(uint cs_pin) {
         ;
     }
 
-    if (clock_get_hz(clk_sys) >= 120000000) {
-        // Set PSRAM timing for APS6404:
-        // - Max select assumes a sys clock speed >= 120MHz
-        // - Min deselect assumes a sys clock speed <= 305MHz
-        // - Clkdiv of 2 is OK up to 266MHz.
-        qmi_hw->m[1].timing = 1 << QMI_M1_TIMING_COOLDOWN_LSB |
-            QMI_M1_TIMING_PAGEBREAK_VALUE_1024 << QMI_M1_TIMING_PAGEBREAK_LSB |
-            15 << QMI_M1_TIMING_MAX_SELECT_LSB |
-            5 << QMI_M1_TIMING_MIN_DESELECT_LSB |
-            3 << QMI_M1_TIMING_RXDELAY_LSB |
-            2 << QMI_M1_TIMING_CLKDIV_LSB;
-    } else {
-        // Set PSRAM timing for APS6404:
-        // - Max select assumes a sys clock speed >= 120MHz
-        // - Min deselect assumes a sys clock speed <= 138MHz
-        // - Clkdiv of 1 is OK up to 133MHz.
-        qmi_hw->m[1].timing = 1 << QMI_M1_TIMING_COOLDOWN_LSB |
-            QMI_M1_TIMING_PAGEBREAK_VALUE_1024 << QMI_M1_TIMING_PAGEBREAK_LSB |
-            15 << QMI_M1_TIMING_MAX_SELECT_LSB |
-            2 << QMI_M1_TIMING_MIN_DESELECT_LSB |
-            2 << QMI_M1_TIMING_RXDELAY_LSB |
-            1 << QMI_M1_TIMING_CLKDIV_LSB;
+    // Set PSRAM timing for APS6404
+    //
+    // Using an rxdelay equal to the divisor isn't enough when running the APS6404 close to 133MHz.
+    // So: don't allow running at divisor 1 above 100MHz (because delay of 2 would be too late),
+    // and add an extra 1 to the rxdelay if the divided clock is > 100MHz (i.e. sys clock > 200MHz).
+    const int max_psram_freq = 133000000;
+    const int clock_hz = clock_get_hz(clk_sys);
+    int divisor = (clock_hz + max_psram_freq - 1) / max_psram_freq;
+    if (divisor == 1 && clock_hz > 100000000) {
+        divisor = 2;
+    }
+    int rxdelay = divisor;
+    if (clock_hz / divisor > 100000000) {
+        rxdelay += 1;
     }
 
+    // - Max select must be <= 8us.  The value is given in multiples of 64 system clocks.
+    // - Min deselect must be >= 18ns.  The value is given in system clock cycles - ceil(divisor / 2).
+    const int clock_period_fs = 1000000000000000ll / clock_hz;
+    const int max_select = (125 * 1000000) / clock_period_fs;  // 125 = 8000ns / 64
+    const int min_deselect = (18 * 1000000 + (clock_period_fs - 1)) / clock_period_fs - (divisor + 1) / 2;
+
+    qmi_hw->m[1].timing = 1 << QMI_M1_TIMING_COOLDOWN_LSB |
+        QMI_M1_TIMING_PAGEBREAK_VALUE_1024 << QMI_M1_TIMING_PAGEBREAK_LSB |
+        max_select << QMI_M1_TIMING_MAX_SELECT_LSB |
+        min_deselect << QMI_M1_TIMING_MIN_DESELECT_LSB |
+        rxdelay << QMI_M1_TIMING_RXDELAY_LSB |
+        divisor << QMI_M1_TIMING_CLKDIV_LSB;
+
     // Set PSRAM commands and formats
     qmi_hw->m[1].rfmt =
         QMI_M0_RFMT_PREFIX_WIDTH_VALUE_Q << QMI_M0_RFMT_PREFIX_WIDTH_LSB | \