What about off-loading the CPU to the FPGA

[stan3c]

Hi, srsRAN is quite demanding on the host PC that runs the srsRAN code. It needs many CPU cores, RAM bandwidth, etc. Such a PC is not very difficult to find but it is expensive and not efficient in terms of money and power consumption.
On the other hand the radios that are compatible with srsRAN have very often quite advanced FPGAs that are empty in large part. X3xx or N3xx radios for example have Kintex FPGAs which resources are largely left unused.
So I was wander whether it would be possible to move some parts of the srsRAN code to FPGA and make the whole system to use the computing resources more efficiently? For example, I was always wonder why the receive channel is not demodulated inside the FPGA down to a bit stream? A CPU is more efficient at bit manipulation, while FPGA is more efficient at signal processing such as demodulation.
A similar situation is at the transmit side.
I do not understand why srsRAN has to deliver IQ samples to the radio instead of just bits.
How is it done in the 4G/5G equipment sold by large infrastructure equipment vendors?