USRP X410 Configuration Issues with srsRAN

[zhou-leo]

Hello, I am currently attempting to configure and run srsRAN with a USRP X410 device. I modified the official USRP N310 configuration file since there is no dedicated configuration file for the X410. The specific configuration file is gnb_rf_n310_fdd_n3_20mhz.yml, and I changed 'type=n3xx' to 'type=x4xx'.

When I run the command sudo gnb -c gnb_rf_n310_fdd_n3_20mhz.yml, I encounter an error stating that the attempted master clock rate of 491.52 MHz is not compatible with the FPGA on the USRP X410, which expects a decimation of 2.

The error message is as follows:

~/srsRAN_Project/build/apps/gnb$ sudo gnb -c gnb_rf_n310_fdd_n3_20mhz.yml 
Lower PHY in quad executor mode.

--== srsRAN gNB (commit 583c92b16) ==--

Connecting to AMF on 127.0.1.100:38412
Available radio types: uhd.
[INFO] [UHD] linux; GNU C++ version 9.4.0; Boost_107100; UHD_4.4.0.HEAD-0-g5fac246b
[INFO] [LOGGING] Fastpath logging disabled at runtime.
Making USRP object with args 'type=x4xx,master_clock_rate=491.52e6,send_frame_size=8000,recv_frame_size=8000'
[INFO] [MPMD] Initializing 1 device(s) in parallel with args: mgmt_addr=192.168.10.2,type=x4xx,product=x410,serial=324062A,name=ni-x4xx-324062A,fpga=X4_200,claimed=False,addr=192.168.10.2,master_clock_rate=491.52e6,send_frame_size=8000,recv_frame_size=8000
[ERROR] [RPC] master_clock_rate 491520000.0 is not compatible with FPGA which expected decimation 2
[ERROR] [MPM.PeriphManager] master_clock_rate 491520000.0 is not compatible with FPGA which expected decimation 2
[ERROR] [MPM.RPCServer] init() failed with error: master_clock_rate 491520000.0 is not compatible with FPGA which expected decimation 2
Failed to open device with address 'type=x4xx': RuntimeError: Error during RPC call to `init'. Error message: master_clock_rate 491520000.0 is not compatible with FPGA which expected decimation 2
srsGNB ERROR: Unable to create radio session.

I am quite confused about this error, especially since I am using the official configuration files as a basis. Could anyone please provide some guidance on how to adjust the configuration for the USRP X410? Are there any specific parameters that need to be adjusted to be compatible with the X410's FPGA requirements?

[ismagom]

HI @zhou-leo , please see #150